Device Having Clock Generating Capabilities and a Method for Generating a Clock Signal

1. A method for generating a clock signal, the method comprises: dividing an input clock signal by a first divider to provide a first clock signal; dividing the input clock signal by a second divider to provide a second clock signal; wherein the first clock signal is phase shifted in relation to the second clock signal by half an input clock cycle; wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of delay affecting parameter values; and generating the reconstructed clock signal by applying a logical operation on the first and second clock signals; wherein the reconstructed clock signal has a cycle that equals the input clock cycle; outputting an output clock signal in response to a selection signal that indicates whether to output the first clock signal, the second clock signal or the reconstructed clock signal.

2. The method according to claim 1 comprising: dividing the input clock signal by a first divider that comprises a positive edge triggered shift register; and dividing the input clock signal by a second divider that comprises a negative edge triggered shift register; wherein each of the positive edge triggered shift register and negative edge triggered shift register is coupled to a control circuit.

3. The method according to claim 1 comprising generating the reconstructed clock signal by applying a XOR operation on the first and second clock signals.

4. The method according to claim 1 comprising: providing the selection signal to a selection unit that outputs the selected clock signal; applying the logical operation by the reconstruction circuit to provide the reconstructed clock signal to a selection unit delaying the first clock signal by a first delay circuit that has an output that is coupled to an input of the selection unit; delaying the second clock signal by a second delay circuit that has an output that is coupled to an input of the selection unit; wherein a delay period of the first delay circuit substantially equals a delay period of the reconstruction circuit and a delay of the second delay circuit over a large range of delay affecting parameter values.

5. The method according to claim 4 wherein each of the first and second delay circuits comprises a logical gate that equals a logical gate of the logical circuit.

6. The method according to claim 1 wherein each of the first delay circuit, the second delay circuit and the reconstruction circuit comprises a XOR logic gate that applies a XOR operation on at least one clock signal.

7. The method according to claim 1 wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of temperatures.

8. The method according to claim 1 wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of voltage supply levels.

9. The method according to claim 1 wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of process variations.

10. The method according to claim 1 wherein the reconstructed clock signal is phase shifted in relation to the input clock signal by an insignificant fraction of an input clock cycle.

11. A device having clock generating capabilities, the device comprises: a first divider, adapted to receive an input clock signal and divide the input clock signal to provide a first clock signal; a second divider, adapted to receive the input clock signal and divide the input clock signal to provide a second clock signal; wherein the first clock signal is phase shifted in relation to the second clock signal by half an input clock cycle; wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of delay affecting parameter values; and a reconstruction circuit, coupled to the first and second divider circuits, adapted to receive the first and second clock signals and apply a logical operation on the first and second clock signals to provide a reconstructed clock signal; and a selection circuit, coupled to the first divider, second divider and reconstruction circuit, adapted to output an output clock signal in response to a selection signal that indicates whether to output the first clock signal, the second clock signal or the reconstructed clock signal.

12. The device according to claim 11 wherein the first divider comprises a positive edge triggered shift register and the second divider comprises a negative edge triggered shift register; wherein each of the positive edge triggered shift register and negative edge triggered shift register is coupled to a control circuit.

13. The device according to claim 11 wherein the reconstruction circuit comprises a XOR logic gate that applies a XOR operation on the first and second clock signals.

14. The device according to claim 11 comprising: a first delay circuit coupled between the first divider and the selection unit; a second delay circuit coupled between the second divider and the selection unit; wherein a delay period of the first delay circuit substantially equals a delay period of the reconstruction circuit and a delay of the second delay circuit over a large range of delay affecting parameter values.

15. The device according to claim 14 wherein each of the first and second delay circuits comprises a logical gate that equals a logical gate of the logical circuit.

16. The device according to claim 11 wherein each of the first delay circuit, the second delay circuit and the reconstruction circuit comprises a XOR logic gate.

17. The device according to claim 11 wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of temperatures.

18. The device according to claim 11 wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of voltage supply levels.

19. The device according to claim 11 wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of process variations.

20. The device according to claim 11 wherein the reconstructed clock signal is phase shifted in relation to the input clock signal by an insignificant fraction of an input clock cycle.