Apparatus and Method for Fairness Arbitration for a Shared Pipeline in a Large Smp Computer System

1. Apparatus comprising; a plurality of priority setting logic elements which controllably pass requests for access to computer system resources through a shared pipeline, said plurality of logic elements comprising; a first element which gates a request for resource access to the shared pipeline; second elements operatively associated with said first element and which receive access requests to be passed through said first element; and third elements which serve as blocking latches, each of said third elements being operatively associated with a corresponding one of said second elements and effective to permit or block a request passing through said second element reaching said first element; and said second and third elements cooperating to latch a second element in a blocked condition blocking the passing of an access request to said first element in the event that a request is pending at another of said second elements.

2. Apparatus according to claim 1 wherein said second elements are organized in a ranked priority scheme and further wherein the cooperation of said second and third elements modifies the ranked priority scheme to favor fairness in access for lower ranked second elements.

3. Apparatus according to claim 1 wherein said logic elements are semiconductor gates.

4. Apparatus according to claim 1 wherein said logic elements are program elements executing on a processor.

5. Apparatus according to claim 1 wherein said logic elements are a series of instructions provided by program media.

6. Apparatus according to claim 1 wherein said plurality of logic elements are arranged in a linked layered structure with said layers being organized in a ranked priority scheme, each layer comprising a set of first, second and third elements associated with the other elements grouped in a common layer, and any request for access passing through successive linked layers as arbitration proceeds first among groups and then across groups.

7. Method comprising; providing a plurality of priority setting logic elements which controllably pass requests for access to computer system resources to a shared pipeline; receiving access requests to be passed to the shared pipeline at a plurality of first level elements among the plurality of elements; gating a received request to the shared pipeline through a second level element upon arbitration for such gating; selectively permitting or blocking a received request passing through a first level element from reaching the second level element by latching a latch element operatively associated with a corresponding one of the first level elements and effective to permit or block a request passing through the first level element reaching the second level element; the first level and latch elements cooperating to block the passing of an access request to the second level element in the event that a request is pending at another of the first level elements.

8. Method according to claim 7 wherein the first level elements are organized in a ranked priority scheme and further wherein the cooperation of the first level and latch elements modifies the ranked priority scheme to favor fairness in access for lower ranked first level elements.

9. Method according to claim 8 implemented in logic elements which are semiconductor gates.

10. Method according to claim 8 implemented in logic elements which are program elements executing on a processor.

11. Method according to claim 7 wherein the plurality of logic elements are arranged in a linked layered structure with layers organized in a ranked priority scheme, each layer comprising a set of first, second and latch elements associated with the other elements grouped in a common layer, and any request for access passing through successive linked layers as arbitration proceeds first among groups and then across groups.

12. Method according to claim 7 wherein the method steps are performed as part of a service provided.

13. Method according to claim 12 implemented in logic elements which are semiconductor gates.

14. Method according to claim 12 implemented in logic elements which are program elements executing on a processor.

15. Method according to claim 7 wherein the method is embodied in a series of instructions provided by program media.

16. Method comprising; producing computer executable program code; providing the program code to be deployed to and executed on a computer system which has a plurality of priority setting logic elements which controllably pass requests for access to computer system resources to a shared pipeline; the program code comprising instructions which: receive access requests to be passed to the shared pipeline at a plurality of first level elements among the plurality of elements; gate a received request to the shared pipeline through a second level element upon arbitration for such gating; selectively permit or block a received request passing through a first level element from reaching the second level element by latching a latch element operatively associated with a corresponding one of the first level elements and effective to permit or block a request passing through the first level element reaching the second level element; the first level and latch elements cooperating to block the passing of an access request to the second level element in the event that a request is pending at another of the first level elements.

17. Method according to claim 16 wherein the first level elements are organized in a ranked priority scheme and further wherein the cooperation of the first level and latch elements modifies the ranked priority scheme to favor fairness in access for lower ranked first level elements.

18. Method according to claim 17 implemented in logic elements which are semiconductor gates.

19. Method according to claim 17 implemented in logic elements which are program elements executing on a processor.

20. Method according to claim 16 wherein the plurality of logic elements are arranged in a linked layered structure with layers organized in a ranked priority scheme, each layer comprising a set of first, second and latch elements associated with the other elements grouped in a common layer, and any request for access passing through successive linked layers as arbitration proceeds first among groups and then across groups.