7694300

Inter-Process Interference Elimination

PublishedApril 6, 2010
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
20 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A computer configured with an operating system, the computer comprising: a processor configured to execute processor-executable instruction streams of one or more operating-system processes; a memory configured to hold one or more operating-system processes as the processor-executable instruction streams of the one or more processes are executed by a processor; an inter-process interference eliminator configured to: analyze the processor-executable instruction stream of a subject operating-system process, which is one of the one or more operating-system processes, to determine if the subject process, when executed, has a potential to interfere with another executing process in the memory; in response to a determination that the subject process, when executed, has the potential to interfere with another executing process in the memory, adjust the processor-executable instruction stream of the subject process to eliminate that potential interference, wherein the processor is configured to concurrently address memory holding two or more operating-system processes as the processor-executable instruction streams of the two or more processes are executed by a processor.

2

2. A computer as recited in claim 1 , wherein the inter-process interference eliminator is further configured to perform the adjustment a priori execution of the processor-executable instruction stream of the subject process.

3

3. A computer as recited in claim 1 , wherein the inter-process interference eliminator is further configured to perform the adjustment during execution of the processor-executable instruction stream of the subject process.

4

4. A computer as recited in claim 1 , wherein the concurrently addressing memory holding two or more operating-system processes is based on a run-time or administrative policy.

5

5. A computer as recited in claim 1 , wherein the inter-process interference eliminator is further configured to perform the analysis a priori execution of the processor-executable instruction stream of the subject process.

6

6. A computer as recited in claim 1 , wherein the inter-process interference eliminator is further configured to perform the analysis during execution of the processor-executable instruction stream of the subject process.

7

7. A computer as recited in claim 1 , wherein one or more actions that adjust the processor-executable instruction stream of the subject process to eliminate that potential interference comprise modifying the processor-executable instruction stream of the subject process.

8

8. A computer as recited in claim 7 , wherein the processor-executable instruction steam is modified to maintain the property of type safety.

9

9. One or more computer storage media having processor-executable instructions that, when executed by at least one processor, perform acts comprising: obtaining one or more operating-system processes, each process comprising a processor-executable instruction stream; determining whether a subject operating-system process, when executing, has a potential to interfere with another operating-system process while both processes are executing, the subject operating-system process being one of the one or more operating-system processes.

10

10. One or more computer storage media as recited in claim 9 , the determining act being performed a priori execution of the processor-executable instruction stream of the subject operating-system process.

11

11. One or more computer storage media as recited in claim 9 , the determining act being performed during execution of the processor-executable instruction stream of the subject operating-system process.

12

12. One or more computer storage media as recited in claim 9 further comprising, in response to a determination that the subject operating-system process, when executed, has the potential to interfere with another executing process, adjusting the processor-executable instruction stream of the subject operating-system process to eliminate that potential interference.

13

13. One or more computer storage media as recited in claim 12 , the adjusting act being performed a priori execution of the processor-executable instruction stream of the subject operating-system process.

14

14. One or more computer storage media as recited in claim 12 , the adjusting act being performed during execution of the processor-executable instruction stream of the subject operating-system process.

15

15. One or more computer storage media as recited in claim 9 , further comprising executing two or more operating-system processes within a common processor-addressable space in a memory.

16

16. One or more computer storage media having processor-executable instructions that, when executed by at least one processor, perform acts comprising: obtaining one or more operating-system processes, each process comprising a processor-executable instruction stream; determining whether a subject operating-system process, when executing, has a potential to interfere with another operating-system process while both processes are executing within a common processor-addressable space in a memory, the subject operating-system process being one of the one or more operating-system processes.

17

17. One or more computer storage media as recited in claim 16 , the determining act being performed a priori execution of the processor-executable instruction stream of the subject operating-system process.

18

18. One or more computer storage media as recited in claim 16 , the determining act being performed during execution of the processor-executable instruction stream of the subject operating-system process.

19

19. One or more computer storage media as recited in claim 16 further comprising, in response to a determination that the subject operating-system process, when executed, has the potential to interfere with another executing process, adjusting the processor-executable instruction stream of the subject operating-system process to eliminate that potential interference.

20

20. One or more computer storage media as recited in claim 19 , the adjusting act being performed a priori or during execution of the processor-executable instruction stream of the subject operating-system process.

Patent Metadata

Filing Date

Unknown

Publication Date

April 6, 2010

Inventors

Galen C. Hunt
James R. Larus
John D. DeTreville
Michael B. Jones
Trishul A. Chilimbi

Want to explore more patents?

Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.

Citation & reuse

Analysis on this page is generated by Patentable — an AI-powered patent intelligence platform. AI-generated summaries, explanations, and analysis may be reused with attribution and a visible link back to the canonical URL below. Patent abstracts and claims are USPTO public domain.

Cite as: Patentable. “INTER-PROCESS INTERFERENCE ELIMINATION” (7694300). https://patentable.app/patents/7694300

© 2026 Patentable. All rights reserved.

Patentable is a research and drafting-assistant tool, not a law firm, and does not provide legal advice. Documents we generate are drafts for review by a licensed patent attorney.