Semiconductor Integrated Circuit and Method of Designing Layout of the Same

1. A semiconductor integrated circuit comprising: a first boundary cell having a first power source wiring, a second power source wiring and a first pseudo power source wiring; a first circuit cell having a third power source wiring connected with the first power source wiring, a second pseudo power source wiring connected with the first pseudo power source wiring, and a first circuit formed of a first circuit transistor; and a first switching transistor having a first electrode connected with the second power source wiring, a second electrode connected with the first pseudo power source wiring, and a gate electrode, wherein the first switching transistor is operated to be turned “ON” and “OFF” according to a control signal inputted to the gate electrode of the first switching transistor and an absolute value of a threshold voltage of the first switching transistor is larger than an absolute value of a threshold voltage of the first circuit transistor.

2. The semiconductor integrated circuit according to claim 1 , wherein the first switching transistor is located in the first boundary cell.

3. The semiconductor integrated circuit according to claim 1 , further comprising: a second circuit cell having a fourth power source wiring connected with the third power source wiring, a third pseudo power source wiring connected with the second pseudo power source wiring, and a second circuit formed of a second circuit transistor; a second boundary cell having a fifth power source wiring connected with the fourth power source wiring, a fourth pseudo power source wiring connected with the third pseudo power source wiring, and a sixth power source wiring; and a second switching transistor having a first electrode connected with the sixth power source wiring, a second electrode connected with the fourth pseudo power source wiring, and a gate electrode, wherein the second switching transistor is operated to be turned “ON” and “OFF” according to the control signal inputted to the gate electrode of the second switching transistor, an absolute value of a threshold voltage of the second switching transistor is larger than an absolute value of a threshold voltage of the first and second circuit transistors, and the first and second circuit cells are located between first and second boundary cells.

4. The semiconductor integrated circuit according to claim 3 , wherein the second switching transistor is located in the second boundary cell.

5. The semiconductor integrated circuit according to claim 1 , further comprising: a second circuit cell having a fourth power source wiring connected with the third power source wiring, a third pseudo power source wiring connected with the second pseudo power source wiring, and a second circuit formed of a second circuit transistor; and a second boundary cell having a fifth power source wiring connected with the fourth power source wiring, a fourth pseudo power source wiring connected with the third pseudo power source wiring, and a sixth power source wiring connected with the second power source wiring, wherein an absolute value of a threshold voltage of the first switching transistor is larger than an absolute value of a threshold voltage of the second circuit transistor, and the first and second circuit cells are located between first and second boundary cells.

6. The semiconductor integrated circuit according to claim 1 , wherein the first circuit cell is a rectangular shape and has first edge, second edge opposite to the first edge, and third and fourth edges between the first and second edges and opposite to each other, the third power source wiring is along with the first edge, the second pseudo power source wiring is along with the second edge, the first circuit is located between the third power source wiring and the second pseudo power source wiring, and the first boundary cell faces the third edge of the first circuit cell.

7. The semiconductor integrated circuit according to claim 6 , further comprising a second circuit cell having a fourth power source wiring line, wherein the second circuit cell is located along with the first edge of the first circuit cell, and the third power source wiring of the first circuit cell and the fourth power source wiring of the second circuit cell share a single power source wiring.

8. The semiconductor integrated circuit according to claim 1 , further comprising: a power source isolating region disposed between the second power source wiring and the first pseudo power source wiring.

9. A semiconductor integrated circuit comprising: a switching transistor cell having a first power source wiring, a second power source wiring, a first pseudo power source wiring, and switching transistor; and a circuit cell having a third power source wiring connected with the first power source wiring, a second pseudo power source wiring connected with the first pseudo power source wiring, and a circuit formed of a circuit transistor, wherein the switching transistor having a first electrode connected with the second power source wiring, a second electrode connected with the first pseudo power source wiring, and a gate electrode, the switching transistor is operated to be turned “ON” and “OFF” according to a control signal inputted to the gate electrode of the switching transistor and an absolute value of a threshold voltage of the switching transistor is larger than an absolute value of a threshold voltage of the circuit transistor.

10. The semiconductor integrated circuit according to claim 9 , wherein the circuit cell is a rectangular shape and has first edge, second edge opposite to the first edge, and third and fourth edges between the first and second edges opposite to each other, the third power source wiring is along with the first edge, the second pseudo power source wiring is along with the second edge, the circuit is located between the third power source wiring and the second pseudo power source wiring, and the switching transistor cell faces the third edge of the circuit cell.

11. The semiconductor integrated circuit according to claim 9 , further comprising: a power source isolating region disposed between the second power source wiring and the first pseudo power source wiring.

12. A method of designing a layout of a semiconductor integrated circuit, comprising: disposing a boundary cell having a first power source wiring, a second power source wiring and a first pseudo power source wiring; disposing, a circuit cell which includes a third power source wiring connected with the first power source wiring, a second pseudo power source wiring connected with the first pseudo power source wiring, and a circuit formed of a circuit transistor; and generating, by a computer, a switching transistor, which has an absolute value of a threshold voltage larger than an absolute value of a threshold voltage of the circuit transistor, which is operated to be turned “ON” and “OFF” according to a control signal inputted to a gate of the switching transistor, which electrically connects the first pseudo power source wiring to the second power source wiring when the switching transistor is turned “ON,” and which electrically disconnects the first pseudo power source wirings from the second power source wiring when the switching transistor is turned “OFF.”

13. The method according to claim 12 , wherein the switching transistor is located in the boundary cell.

14. The method according to claim 12 , wherein the boundary cell has a power source isolating region disposed between the second power source wiring and the first pseudo power source wiring.

15. A method of designing a layout of a semiconductor integrated circuit, comprising: disposing a switching transistor cell having a first power source wiring, a second power source wiring, a first pseudo power source wiring, and switching transistor; and disposing, by a computer, a circuit cell having a third power source wiring connected with the first power source wiring, a second pseudo power source wiring connected with the first pseudo power source wiring, and a circuit formed of a circuit transistor, wherein the switching transistor having a first electrode connected with the second power source wiring, a second electrode connected with the first pseudo power source wiring, and a gate electrode, the switching transistor is operated to be turned “ON” and “OFF” according to a control signal inputted to the gate electrode of the switching transistor and an absolute value of a threshold voltage of the switching transistor is larger than an absolute value of a threshold voltage of the circuit transistor.

16. The method according to claim 15 , wherein the switching transistor cell has a power source isolating region which is disposed between the second power source wiring and the first pseudo power source wiring.