Pseudo Lru Algorithm for Hint-Locking During Software and Hardware Address Translation Cache Miss Handling Modes

1. A method of updating entries in a table used to indicate recent use of entries in an address translation cache in order to guide replacement, comprising: detecting that a request for address translation hits in the address translation cache; determining if the request for address translation hit on a hint locked entry of the address translation cache; and updating an entry in the table only if software address translation cache miss handling is disabled.

2. The method of claim 1 , wherein: the address translation cache is a set associative cache with each set having multiple ways or a fully associative cache with each set having multiple ways.

3. The method of claim 1 , wherein determining if the request for address translation hit on a hint locked way comprises checking one or more hint lock bits.

4. The method of claim 1 , wherein the entry in the table is updated only if the request for address translation hit on an entry that is not hint locked.

5. A processor, comprising: an address translation cache; a table holding entries indicating the recent use of entries in the address translation cache; and logic configured to detect that a request for address translation hits in the address translation cache, determine if the request for address translation hit on a hint locked entry of the address translation cache, and update entries in the table only if software address translation cache miss handling is disabled.

6. The processor or claim 5 , wherein the logic is further configured to: fetch data in response to an address translation request that misses in the address translation cache; retrieve an entry from the table; generate a selection value by modifying the retrieved entry based on corresponding hint lock bits; and use the generated selection value to select a way in the address translation cache for replacement with the fetched data.

7. The processor of claim 6 , wherein the logic is further configured to: retrieve an entry from the table and ignore the hint lock bits if all the hint lock bits indicate all the ways are hint locked and select a way for replacement based on an entry from the table.

8. The processor of claim 6 , wherein: the address translation cache is a set associative cache, with each set having multiple ways or a fully associative cache; and the logic is configured to determine if the request for address translation hits on a hint locked way.

9. The processor of claim 6 , wherein the logic is configured to determine if the request for address translation hit on a hint locked way by checking one or more hint lock bits.

10. The processor of claim 5 , wherein the logic is configured to update entries in the table only if the address translation cache hits on an entry that is not hint locked.