Multiple-Core, Multithreaded Processor with Flexible Error Steering Mechanism

1. An integrated circuit, comprising: a plurality of processor cores, wherein each of said processor cores is associated with a respective plurality of threads, and wherein each of said processor cores is configured to issue a first instruction from one of said respective plurality of threads during one execution cycle and to issue a second instruction from another one of said respective plurality of threads during a successive execution cycle; and an error processing unit coupled to said processor cores and configured to detect an error condition corresponding to a data element external to said plurality of processor cores, wherein for any given error condition corresponding to the data element, detection of the given error condition occurs independent from operation of said processor cores; wherein, in response to detecting said error condition, said error processing unit is further configured to convey an indication of said error condition to a selected one of said processor cores dependent upon an identifier of said selected processor core, wherein said indication includes an identifier of a selected thread executable on said selected processor core; and wherein said identifiers of said selected processor core and said selected thread are programmable such that: for each given detected error condition that is reportable, said error processing unit is configured to convey an indication of said given detected error condition to said selected processor core and said selected thread; and after identifiers of said selected processor core or said selected thread are programmed that differ from previously programmed identifiers, said error processing unit is configured to convey said indication of said given detected error condition to a different selected processor core or a different selected thread, wherein the different selected processor core is distinct from a previously selected processor core, and wherein the different selected thread is distinct from a previously selected thread, such that on different occasions, said error processing unit is configured to send a same indication of a same detected error condition to different ones of said processor cores or said threads, depending on how said identifiers of said selected processor core and said selected thread are programmed.

2. The integrated circuit as recited in claim 1 , wherein said indication of said error condition includes an error trap indication, and wherein in response to receiving said error trap indication, said selected processor core is configured to execute an error trap handler associated with said selected thread.

3. The integrated circuit as recited in claim 1 , wherein said data element includes a data transmission element.

4. The integrated circuit as recited in claim 1 , wherein said data element includes a data storage element.

5. The integrated circuit as recited in claim 4 , wherein said data storage element includes a random access memory (RAM).

6. The integrated circuit as recited in claim 4 , wherein said data storage element includes a content-addressable memory (CAM).

7. The integrated circuit as recited in claim 4 , wherein said data storage element includes one of a first-in, first-out (FIFO) queue or a last-in, first-out (LIFO) queue.

8. The integrated circuit as recited in claim 1 , wherein said error processing unit includes an error steering register configured to store said identifiers of said selected processor core and said selected thread, and wherein said error steering register is software programmable.

9. The integrated circuit as recited in claim 1 , wherein said error processing logic is coupled to said plurality of processor cores via a packet-based interface, wherein said error processing logic conveying said indication of said error condition to said selected processor core includes said error processing logic conveying a packet including an indication of said identifier of said selected thread to said selected processor core via said packet-based interface.

10. A method, comprising: selecting one of a plurality of processor cores to perform processing of an error condition occurring in a data element external to said plurality of processor cores, wherein each of said processor cores is associated with a respective plurality of threads, and wherein each of said processor cores is configured to issue a first instruction from one of said respective plurality of threads during one execution cycle and to issue a second instruction from another one of said respective plurality of threads during a successive execution cycle; selecting one of said respective plurality of threads associated with said selected processor core to perform processing of said error condition; programming respective identifiers of said selected processor core and said selected thread, such that for each given detected error condition that is reportable, an indication of said given detected error condition is conveyed to said selected processor core and said selected thread, and such that after identifiers of said selected processor core or said selected thread are programmed that differ from previously programmed identifiers, said indication of said given detected error condition is conveyed to a different selected processor core or a different selected thread, wherein the different selected processor core is distinct from a previously selected processor core, and wherein the different selected thread is distinct from a previously selected thread; detecting said error condition corresponding to said data element external to said plurality of processor cores, wherein for any given error condition corresponding to the data element, detecting the error condition occurs independent from operation of said processor cores; and conveying an indication of said error condition to said selected processor core dependent upon said programmed respective identifier of said selected processor core, such that on different occasions, a same indication of a same detected error condition is conveyed to different ones of said processor cores or said threads, depending on how said identifiers of said selected processor core and said selected thread are programmed.

11. The method as recited in claim 10 , wherein said indication of said error condition includes an error trap indication, and wherein in response to receiving said error trap indication, said selected processor core is configured to execute an error trap handler associated with said selected thread.

12. The method as recited in claim 10 , wherein said data element includes a data transmission element.

13. The method as recited in claim 10 , wherein said data element includes a data storage element.

14. The method as recited in claim 13 , wherein said data storage element includes a random access memory (RAM).

15. The method as recited in claim 13 , wherein said data storage element includes a content-addressable memory (CAM).

16. The method as recited in claim 13 , wherein said data storage element includes one of a first-in, first-out (FIFO) queue or a last-in, first-out (LIFO) queue.

17. The method as recited in claim 10 , wherein programming said respective identifiers of said selected processor core and said selected thread includes executing software on one of said processor cores to program an error steering register configured to store said identifiers of said selected processor core and said selected thread.

18. The method as recited in claim 10 , wherein conveying said indication of said error condition to said selected processor core includes conveying a packet including an indication of said identifier of said selected thread to said selected processor core via a packet-based interface.

19. A system, comprising: a system memory; and a processor coupled to said system memory, wherein said processor includes: a plurality of processor cores, wherein each of said processor cores is associated with a respective plurality of threads, and wherein each of said processor cores is configured to issue a first instruction from one of said respective plurality of threads during one execution cycle and to issue a second instruction from another one of said respective plurality of threads during a successive execution cycle; and an error processing unit coupled to said processor cores and configured to detect an error condition corresponding to a data element external to said plurality of processor cores, wherein for any given error condition corresponding to the data element, detection of the given error condition occurs independent from operation of said processor cores; wherein, in response to detecting said error condition, said error processing unit is further configured to convey an indication of said error condition to a selected one of said processor cores dependent upon an identifier of said selected processor core, wherein said indication includes an identifier of a selected thread executable on said selected processor core; and wherein said identifiers of said selected processor core and said selected thread are programmable such that: for each given detected error condition that is reportable, said error processing unit is configured to convey an indication of said given detected error condition to said selected processor core and said selected thread; and after identifiers of said selected processor core or said selected thread are programmed that differ from previously programmed identifiers, said error processing unit is configured to convey said indication of said given detected error condition to a different selected processor core or a different selected thread, wherein the different selected processor core is distinct from a previously selected processor core, and wherein the different selected thread is distinct from a previously selected thread, such that on different occasions, said error processing unit is configured to send a same indication of a same detected error condition to different ones of said processor cores or said threads, depending on how said identifiers of said selected processor core and said selected thread are programmed.

20. The processor as recited in claim 19 , wherein said indication of said error condition includes an error trap indication, and wherein in response to receiving said error trap indication, said selected processor core is configured to execute an error trap handler associated with said selected thread.