Legal claims defining the scope of protection, as filed with the USPTO.
1. A processing device comprising: a scan chain comprising an input, an output, and a plurality of latches coupled in series between the input and the output, the plurality of latches comprising a first latch having a reset input to receive a scan reset signal, a data input, and a data output, the first latch configured to reset a first latched data of the first latch to a predetermined value in response to an assertion of the scan reset signal; and a scan controller comprising an input to receive a test mode signal and an output coupled to the reset input of the first latch to provide the scan reset signal, the scan controller configured to assert the scan reset signal in response to an assertion of the test mode signal, the assertion of the test mode signal to enable the processing device to enter a scan test mode to read information that is present in latches of the scan chain other than the first latch prior to the assertion of the test mode signal.
2. The processing device of claim 1 , wherein the scan chain further comprises a second latch having a reset input to receive the scan reset signal, a data input coupled to the output of the first latch, and a data output, the second latch configured to reset a second latched data of the second latch to the predetermined value in response to an assertion of the scan reset signal.
3. The processing device of claim 1 , further comprising: a random access memory comprising an output coupled to the data input of the first latch; and a reset module configured to clear information stored in the random access memory in response to the assertion of the scan reset signal.
4. The processing device of claim 3 , wherein: the reset module is configured to assert an event trigger signal in response to clearing the information stored in the random access; and the scan controller is configured to assert the scan enable signal in response to the assertion of the event trigger signal.
5. The processing device of claim 1 , wherein the scan controller comprises an input to receive a reset signal that is to reset the processing device, the scan controller configured to assert the scan reset signal in response to an assertion of the reset signal.
6. The processing device of claim 1 , further comprising: a state machine comprising a reset input to receive the scan reset signal, a data input coupled to the data output of the first latch, and a data output, the state machine configured to reset a data stored at the state machine to the predetermined value in response to an assertion of the scan reset signal.
7. The processing device of claim 1 , wherein: the first latch further comprises an input to receive a scan exit signal, the first latch configured to reset the latched data to the predetermined value in response to an assertion of the scan exit signal; and the scan controller is configured to assert the scan exit signal in response to a deassertion of the test mode signal, the deassertion of the test mode signal disabling the scan test mode of the processing device.
8. The processing device of claim 7 , further comprising: a state machine comprising a reset input to receive the scan exit signal, a data input coupled to the data output of the first latch, and a data output, the state machine configured to reset a data stored at the state machine to the predetermined value in response to an assertion of the scan exit signal.
9. The processing device of claim 1 , wherein the first latch is configured to latch a secure key data.
10. The processing device of claim 1 , wherein: the first latch comprises a scan input to receive a scan enable signal, the first latch configured to enable shifting of data via the first latch in response to an assertion of the scan enable signal; and the scan controller comprises an output configured to assert the scan enable signal in response to an assertion of the test mode signal.
11. The processing device of claim 10 , wherein the scan controller further comprises logic to delay asserting the scan enable signal after the assertion of the test mode signal.
12. A processing device comprising: a scan chain comprising a plurality of latches coupled in series, the plurality of latches comprising a first set of latches to store secure data and a second set of latches to store non-secure data; and a scan controller to reset the first set of latches to a predetermined value and to maintain a latched value at each of the second set of latches subsequent to enabling the processing device to enter a scan test mode and prior to enabling shifting of data in the scan chain.
13. The processing device of claim 12 , wherein the secure data comprises one of a group consisting of: a secure key; and a software-implemented algorithm.
14. The processing device of claim 12 , wherein the scan controller is configured to enable shifting of data in the scan chain subsequent to resetting the first set of latches.
15. The processing device of claim 12 , further comprising: a random access memory comprising an output coupled to a data input of a latch of the first set of latches, the random access memory to store secure data; and a reset module configured to clear the secure data stored in the random access memory in response to enabling the processing device to enter the scan test mode.
16. In a processing device comprising a scan chain comprising a first latch having a reset input to receive a scan reset signal and wherein the first latch is configured to reset a first latched data of the first latch to a predetermined value in response to an assertion of the scan reset signal, a method comprising: receiving an asserted test mode signal to enable the processing device to enter a scan test mode to read data that is present in latches of the scan chain other than the first latch prior to the assertion of the test mode signal; and asserting the scan reset signal in response to receiving the asserted test mode signal and prior to enabling shifting of data at the scan chain.
17. The method of claim 16 , wherein the processing device further comprises a random access memory having an output coupled to the first latch, the method further comprising: clearing data stored in the random access memory in response to the processing device entering the scan test mode.
18. The method of claim 16 , further comprising: asserting a scan enable signal in response to asserting the scan reset signal, the scan enable signal enabling shifting of data in the scan chain; and shifting data in the scan chain in response to the assertion of the scan enable signal.
19. The method of claim 18 , further comprising: deasserting the scan enable signal to disable shifting of data in the scan chain; and asserting the scan reset signal in response to deasserting the scan enable signal.
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May 25, 2010
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