Legal claims defining the scope of protection, as filed with the USPTO.
1. A computer comprising: plural word-length registers including a result register having plural subword locations; an instruction decoder for decoding computer-executable program instructions, said program instructions being program-instruction instances of instruction-set instructions of an instruction set; and an execution unit for executing said program instructions; said instruction set including a subset of one or more parallel-subword instruction-subset instructions all program-instruction instances of which yield the same subword-length operation result given the same word-length operands, said subset being characterized in that for each of said plural subword locations there exists a series of program-instruction instances of said instruction-subset instructions for which a last program-instruction instance of said series writes a subword-length operation result into that subword location, a first program-instruction instance of said series writing said subword-length operation result into said result register.
2. A computer as recited in claim 1 wherein said subset includes plural instruction-subset instructions respectively corresponding to said plural subword locations, each program-instruction instance of said instruction-subset instructions causing the result of the associated operation to be stored at the corresponding selectable location.
3. A computer as recited in claim 2 wherein each of said plural instruction-subset instructions overwrites bit positions within non-selected locations of said result register and within the selected location.
4. A computer as recited in claim 2 wherein each of said plural instruction-subset instructions leaves intact contents of bit positions within non-selected locations of said result register but not bit positions within the selected location.
5. A computer as recited in claim 1 wherein said subset includes a characterizing instruction-set instruction program-instruction instances of which generate plural replicas of said result to be stored in respective ones of said selectable locations.
6. A computer as recited in claim 1 wherein said subset includes an instruction-subset instruction that causes said result to be stored in a subword location of said result register that depends on the number of times said instruction is consecutively iterated.
7. A computer as recited in claim 1 wherein at least one pair of said plural subword locations overlap.
8. A computer as recited in claim 1 wherein said plural subword locations are mutually exclusive.
9. Computer-readable memory comprising: a program of computer-executable program instructions, said program instructions being program-instruction instances of instruction-set instructions including a subset of parallel-subword instruction-set instruction all program-instruction instances of which yield the same subword length result for any given set of operands, said program including first and second parallel-subword program-instruction instances, said first parallel-subword program-instruction instance storing a first subword-length result in a first subword location of a result register, said second parallel-subword program-instruction instance storing a second subword-length result in said result register so that said first and second results are stored concurrently in said result register, said second parallel-subword program-instruction instance storing either said first subword-length result or said second subword length result in a second subword location of said result register.
10. Computer-readable memory as recited in claim 9 wherein said subset includes plural instruction-set instructions program-instruction instances of which store subword-length results in respective different subword locations of the same result register.
11. Computer-readable memory as recited in claim 10 wherein each of said plural program-instruction instances overwrites bit positions within non-selected locations and within its respective subword location.
12. Computer-readable memory as recited in claim 10 wherein each of said plural program-instruction instances leaves intact bit positions within non-respective subword locations of said result register.
13. Computer-readable memory as recited in claim 9 wherein said subset includes a characterizing instruction-set instruction a program-instruction instance of which generates plural replicas of said subword-length result to be stored in plural subword locations of said result register.
14. Computer-readable memory as recited in claim 9 wherein said subset includes an instruction instance that causes said result to be stored in a subword location of said result register that depends on the number of times said instruction instance is iterated.
15. Computer-readable memory as recited in claim 9 wherein at least one pair of said subword locations overlap.
16. Computer-readable memory as recited in claim 9 wherein said subword locations are mutually exclusive.
17. A microprocessor comprising an instruction decoder for decoding and an execution unit for executing program-instruction instances of instruction-set instructions of an instruction set, said instruction set including a subset of parallel subword instruction-subset instructions that collectively provide for a result of an associated characterizing parallel-subword operation to be stored at any selected one of plural result-register subword locations, wherein each program instruction instance of said plural instruction-subset instructions leaves intact bit positions within non-selected locations but not within the selected location.
18. Computer-readable memory encoded with a program of program-instruction instances of instruction-set instructions of an instruction set including a subset of one or more parallel-subword instruction-subset instructions program-instruction instances of which yield the same subword length result for any given operands, a first parallel-subword program-instruction instance of at least one of said instruction subset instructions writing a first subword-length result in a first subword location of a result register, a second parallel-subword program-instruction instance of at least one of said instruction-subset instructions writing a second subword-length result in said result register so that said first and second results are stored concurrently in said result register, said second parallel-subword program-instruction instance writing either said first subword-length result or said second subword length result in a second subword location of said result register.
19. A computer as recited in claim 1 wherein said subset includes a first instruction-subset instruction program-instruction instances of which specify as an argument a subword location for writing said subword-length result.
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June 1, 2010
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