Periphery Clock Distribution Network for a Programmable Logic Device

1. A signal network on a programmable logic device for distributing clock-type signals from peripheral input/output blocks of said programmable logic device to other portions of said programmable logic device, said signal network comprising: a device-wide dedicated, low-skew clock-type signal distribution network on said programmable logic device, arranged so that distances traveled by a signal from an entry point of said device-wide dedicated, low-skew clock-type signal distribution network to any destination on said programmable logic device are substantially equal; and a second dedicated clock-type signal distribution network on said programmable logic device, comprising: a first dedicated clock-type signal bus on said programmable logic device separate from said device-wide dedicated, low-skew clock-type signal distribution network, and having an end at a first location adjacent a first group of said peripheral input/output blocks, and a first plurality of dedicated clock-type signal lines on said programmable logic device, each dedicated clock-type signal line in said first plurality of said dedicated clock-type signal lines being separate from said device-wide dedicated, low-skew clock-type signal distribution network, having a first dedicated connection at one end thereof to a respective one of said peripheral input/output blocks in said first group of peripheral input/output blocks, and being connected at another end thereof to said first dedicated clock-type signal bus substantially at said first location; wherein: said first dedicated clock-type signal bus extends from said first location to a first clock distribution spine on said programmable logic device.

2. The signal network of claim 1 wherein said first clock distribution spine extends over at least a substantial portion of said programmable logic device.

3. The signal network of claim 2 wherein said first clock distribution spine is a portion of a larger clock distribution network of said programmable logic device.

4. The signal network of claim 3 wherein said larger clock distribution network is said device-wide dedicated, low-skew clock-type signal distribution network of said programmable logic device.

5. The signal network of claim 3 wherein said larger clock distribution network comprises a second clock distribution spine and said dedicated clock-type signal bus extends also to said second clock distribution spine.

6. The signal network of claim 5 further comprising a selectable connection between said dedicated clock-type signal bus and each of said first and second clock distribution spines.

7. The signal network of claim 1 wherein said programmable logic device comprises a second clock distribution spine and said dedicated clock-type signal bus extends also to said second clock distribution spine.

8. The signal network of claim 7 further comprising a selectable connection between said dedicated clock-type signal bus and each of said first and second clock distribution spines.

9. The signal network of claim 1 further comprising a selectable connection between said dedicated clock-type signal bus and said first clock distribution spine.

10. The signal network of claim 1 wherein said second dedicated clock-type signal distribution network further comprises a selectable connection between said plurality of dedicated clock-type signal lines and said dedicated clock-type signal bus.

11. The signal network of claim 1 wherein said second dedicated clock-type signal distribution network further comprises: a second dedicated clock-type signal bus on said programmable logic device separate from said device-wide dedicated, low-skew clock-type signal distribution network, and having an end at a second location adjacent a second group of said peripheral input/output blocks; and a second plurality of dedicated clock-type signal lines on said programmable logic device, each dedicated clock-type signal line in said second plurality of dedicated clock-type signal lines being separate from said device-wide dedicated, low-skew clock-type signal distribution network, having a second dedicated connection at one end thereof to a respective one of said peripheral input/output blocks in said second group of peripheral input/output blocks, and being connected at another end thereof to said second dedicated clock-type signal bus substantially at said second location; wherein: said second dedicated clock-type signal bus extends from said second location to a second clock distribution spine on said programmable logic device.

12. The signal network of claim 11 wherein said second clock distribution spine extends over at least a substantial portion of said programmable logic device.

13. The signal network of claim 12 wherein said first and second clock distribution spines are portions of a single larger clock distribution network of said programmable logic device.

14. The signal network of claim 13 wherein said single larger clock distribution network is said device-wide dedicated, low-skew clock-type signal distribution network of said programmable logic device.

15. The signal network of claim 12 wherein each of said first and second clock distribution spines is a portion of a respective larger clock distribution network of said programmable logic device.

16. The signal network of claim 15 wherein at least one said respective larger clock distribution network is said device-wide dedicated, low-skew clock-type signal distribution network of said programmable logic device.

17. The signal network of claim 11 wherein at least one respective one of said first and second locations is located substantially at a midpoint relative to its respective one of said first and second groups of peripheral input/output blocks; whereby: for each respective peripheral input/output block in said respective one of said first and second groups of peripheral input/output blocks, there is at least one other one of said peripheral input/output blocks that is substantially equally distant from said respective one of first and second locations.

18. The signal network of claim 1 wherein: said programmable logic device further comprises programmable interconnect for programmably routing signals within and among said peripheral input/output blocks and said other portions; and said at least one wide-area, low-skew signal network is separate from said programmable interconnect.

19. A programmable logic device comprising: regions of programmable logic; a plurality of peripheral input/output blocks; programmable interconnect for programmably routing signals within and among said regions of programmable logic and said plurality of peripheral input/output blocks; at least one wide-area, low-skew signal network on said programmable logic device for distributing clock-type signals within said programmable logic device, arranged so that distances traveled by a signal from an entry point of said at least one wide-area, low-skew signal network to any destination on said programmable logic device are substantially equal; and a second signal network on said programmable logic device at least partially separate from said at least one wide-area, low-skew signal network, for distributing clock-type signals from at least one of said peripheral input/output blocks, said second signal network comprising: a first dedicated clock-type signal bus on said programmable logic device separate from said device-wide dedicated, low-skew clock-type signal distribution network, and having an end at a first location adjacent a first group of said peripheral input/output blocks, and a first plurality of dedicated clock-type signal lines on said programmable logic device, each dedicated clock-type signal line in said first plurality of said dedicated clock-type signal lines being separate from said device-wide dedicated, low-skew clock-type signal distribution network, having a first dedicated connection at one end thereof to a respective one of said peripheral input/output blocks in said first group of peripheral input/output blocks, and being connected at another end thereof to said first dedicated clock-type signal bus substantially at said first location; wherein: said first dedicated clock-type signal bus extends from said first location to a first clock distribution spine on said programmable logic device.

20. The programmable logic device of claim 19 wherein said first clock distribution spine extends over at least a substantial portion of said programmable logic device.

21. The programmable logic device of claim 20 wherein said first clock distribution spine is a portion of one of said at least one wide-area, low-skew signal network.

22. The programmable logic device of claim 21 wherein said one of said at least one wide-area, low-skew signal network is a device-wide low-skew clock distribution network of said programmable logic device.

23. The programmable logic device of claim 21 wherein said one of said at least one wide-area, low-skew signal network comprises a second clock distribution spine and said dedicated clock-type signal bus extends also to said second clock distribution spine.

24. The programmable logic device of claim 23 further comprising a selectable connection between said dedicated clock-type signal bus and each of said first and second clock distribution spines.

25. The programmable logic device of claim 19 further comprising a second clock distribution spine, wherein said dedicated clock-type signal bus extends also to said second clock distribution spine.

26. The programmable logic device of claim 25 further comprising a selectable connection between said dedicated clock-type signal bus and each of said first and second clock distribution spines.

27. The programmable logic device of claim 19 further comprising a selectable connection between said dedicated clock-type signal bus and said first clock distribution spine.

28. The programmable logic device of claim 19 wherein said second signal network further comprises a selectable connection between said plurality of dedicated clock-type signal lines and said dedicated clock-type signal bus.

29. The programmable logic device of claim 19 wherein said second signal network further comprises: a second dedicated clock-type signal bus on said programmable logic device separate from said device-wide dedicated, low-skew clock-type signal distribution network, and having an end at a second location adjacent a second group of said peripheral input/output blocks; and a second plurality of dedicated clock-type signal lines on said programmable logic device, each dedicated clock-type signal line in said second plurality of dedicated clock-type signal lines being separate from said device-wide dedicated, low-skew clock-type signal distribution network, having a second dedicated connection at one end thereof to a respective one of said peripheral input/output blocks in said second group of peripheral input/output blocks, and being connected at another end thereof to said second dedicated clock-type signal bus substantially at said second location; wherein: said second dedicated clock-type signal bus extends from said second location to a second clock distribution spine on said programmable logic device.

30. The programmable logic device of claim 29 wherein said second clock distribution spine extends over at least a substantial portion of said programmable logic device.

31. The programmable logic device of claim 30 wherein said first and second clock distribution spines are portions of a single one of said at least one wide-area, low-skew signal network of said programmable logic device.

32. The programmable logic device of claim 31 wherein said single one of said at least one wide-area, low-skew signal network is a device-wide, low-skew clock distribution network of said programmable logic device.

33. The programmable logic device of claim 30 wherein each of said first and second clock distribution spines is a portion of a respective one of said least one wide-area, low-skew signal network of said programmable logic device.

34. The programmable logic device of claim 33 wherein at least one said respective wide-area, low-skew signal network is a device-wide, low-skew clock distribution network of said programmable logic device.

35. The programmable logic device of claim 29 wherein at least one respective one of said first and second locations is located substantially at midpoint relative to its respective one of said first and second groups of peripheral input/output blocks; whereby: for each respective peripheral input/output block in said respective one of said first and second groups of peripheral input/output blocks, there is at least one other one of said peripheral input/output blocks that is substantially equally distant from said respective one of first and second locations.

36. The programmable logic device of claim 19 wherein: said at least one wide-area, low-skew signal network is separate from said programmable interconnect.

37. A programmable logic device including (a) at least one wide-area, low-skew signal network on said programmable logic device, arranged so that distances traveled by a signal from an entry point of said at least one wide-area, low-skew signal network to any destination on said programmable logic device are substantially equal, for distributing clock-type signals within said programmable logic device, (b) a periphery clock network, and (c) a clock spine, wherein (1) the periphery clock network comprises a collection of individual dedicated clock networks on said programmable logic device separate from said wide-area, low-skew signal network, (2) clock signals are driven over at least one of said individual dedicated clock networks from a periphery of the programmable logic device to the clock spine, and (3) each of said individual dedicated clock networks has a dedicated connection to said periphery.

38. The programmable logic device of claim 37 , further comprising: rows of logic regions; and a first number of said individual dedicated clock networks for each of a second number of said rows of logic regions.

39. The programmable logic device of claim 38 wherein said first number is 2 and said second number is 3.

40. The programmable logic device of claim 37 , said programmable logic device further comprising: a plurality of regions, each of said regions including (a) a separate clock spine, said clock spine having two segments, and (b) a separate periphery clock network; wherein: the separate periphery clock network is connected to the two segments of the separate clock spine by at least a multiplexer.

41. The programmable logic device of claim 37 , said programmable logic device further comprising: a plurality of regions, each of said regions including (a) four separate clock spines, each of said clock spines having two segments, and (b) two separate periphery clock networks: wherein: a first one of said separate periphery clock networks is connected to said two segments of each of a first two of said clock spines by at least a first multiplexer; and a second one of said separate periphery clock networks is connected to said two segments of each of a second two of said clock spines by at least a second multiplexer.

42. The programmable logic device of claim 37 further comprising: programmable interconnect for programmably routing signals within and among regions of programmable logic and a plurality of peripheral input/output blocks; wherein: said at least one wide-area, low-skew signal network is separate from said programmable interconnect.

43. A clock-type signal network on a programmable logic device, said clock-type signal network comprising: a device-wide dedicated, low-skew clock-type signal distribution network, arranged so that distances traveled by a clock-type signal from an entry point of said device-wide dedicated, low-skew signal distribution network to any destination on said programmable logic device are substantially equal; a first dedicated clock-type signal bus separate from said device-wide dedicated, low-skew clock-type signal distribution network, the first dedicated clock-type signal bus having an end at a first location adjacent a first group of peripheral input/output blocks on said programmable logic device; and a first plurality of dedicated clock-type signal lines, each dedicated clock-type signal line in said first plurality of said dedicated clock-type signal lines being separate from said device-wide dedicated, low-skew clock-type signal distribution network, having a dedicated connection at one end thereof to a respective one of said peripheral input/output blocks in said first group of peripheral input/output blocks, and being connected at another end thereof to said first dedicated clock-type signal bus substantially at said first location; wherein: said first dedicated clock-type signal bus extends from said first location to said device-wide dedicated, low-skew clock-type signal distribution network.

44. A programmable logic device including (a) a wide-area, low-skew signal network for distributing clock-type signals within said programmable logic device, arranged so that distances traveled by a clock-type signal from an entry point of said wide-area, low-skew signal network to any destination on said programmable logic device are substantially equal, and (b) a periphery clock network, wherein (1) the periphery clock network comprises a collection of individual dedicated clock networks separate from said wide-area, low-skew signal network, (2) clock-type signals are driven over at least one of said individual dedicated clock networks from a periphery of the programmable logic device to the wide-area, low-skew signal network, and (3) each of said individual dedicated clock networks has a dedicated connection to said periphery.