7739632

System and Method of Automated Wire and via Layout Optimization Description

PublishedJune 15, 2010
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
5 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A design structure embodied in a machine readable medium and usable by a computer in a process for designing and manufacturing an integrated circuit, the design structure comprising: a component to determine design parameters of a design layout including wiring placement and dimensions of a non-optimized via layout; a component to provide an optimized via layout comprising vias placed away from edges of the wiring and adjacent vias, wherein a width of the vias is reduced relative to the non-optimized via layout to effectively increase a spacing between adjacent vias or the edges of the wiring and the vias relative to the non-optimized via layout; and a component to at least one of: move the vias away from one another when they are a predetermined distance away from one another; and move the vias when they are a predetermined distance from the edge of the wiring.

2

2. The design structure of claim 1 , wherein the design structure comprises a netlist, which describes the circuit.

3

3. The design structure of claim 1 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

4

4. The design structure of claim 1 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

5

5. A design structure embodied in a computer readable medium and usable by a computer in a process for designing and manufacturing an integrated circuit, the design structure comprising: a component to determine design parameters of a design layout including wiring placement and dimensions of a non-optimized via layout; a component to provide an optimized via layout comprising vias placed away from edges of the wiring and adjacent vias, wherein a width of the vias is reduced relative to the non-optimized via layout, the non-optimized via layout having been stripped from the design layout, to effectively increase a spacing between adjacent vias or the edges of the wiring and the vias relative to the non-optimized via layout; and a component to at least one of: move the vias away from one another when they are a predetermined distance away from one another; and move the vias when they are a predetermined distance from the edge of the wiring.

Patent Metadata

Filing Date

Unknown

Publication Date

June 15, 2010

Inventors

Bette L. BERGMAN REUTER
Howard S. Landis
Anthony K. Stamper
Jeanne-Tania Sucharitaves

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Cite as: Patentable. “SYSTEM AND METHOD OF AUTOMATED WIRE AND VIA LAYOUT OPTIMIZATION DESCRIPTION” (7739632). https://patentable.app/patents/7739632

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