7747992

Methods and Apparatus for Creating Software Basic Block Layouts

PublishedJune 29, 2010
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
28 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method comprising: identifying branch data associated with a plurality of machine accessible instructions; identifying a plurality of basic blocks associated with the branch data; searching for a set of edges comprising a subset of the plurality of basic blocks, wherein each edge in the set of edges obtained by searching shares either a source basic block or a destination basic block with another edge in the set of edges; generating a set of partial layouts from the subset of the plurality of basic blocks included in the set of edges; generating a substantial layout using a particular partial layout selected from the set of partial layouts based on a cost metric comprising an accumulation of individual costs determined for each pair of adjacent basic blocks in a particular sequential ordering of the plurality of basic blocks included in the particular partial layout, wherein the individual cost for each pair of adjacent basic blocks is determined using a first cost metric when the pair of adjacent basic blocks is connected in the particular partial layout and a second cost metric when the pair of adjacent basic blocks is not connected in the particular partial layout; and determining a plurality of modified machine accessible instructions based on the substantial layout.

2

2. The method as defined in claim 1 , wherein the set of edges comprises an equivalence class, and further comprising generating a plurality of sets of partial layouts for a respective plurality of equivalence classes, and wherein generating the substantial layout further comprises combining a selected plurality of least cost partial layouts corresponding respectively to the plurality of equivalence classes, wherein each least cost partial layout is selected for a respective equivalence class from the respective set of partial layouts generated for the respective equivalence class, and wherein the selected least cost partial layout minimizes the cost metric for the set of partial layouts corresponding to the respective equivalence class.

3

3. The method as defined in claim 1 , further comprising: identifying a first edge associated with a first source basic block associated with the plurality of basic blocks; and identifying a second edge associated with a second source basic block associated with the plurality of basic blocks.

4

4. The method as defined in claim 1 , further comprising: identifying a first edge associated with a first destination basic block associated with the plurality of basic blocks; and identifying a second edge associated with a second destination basic block associated with the plurality of basic blocks.

5

5. The method as defined in claim 1 , further comprising simulating execution of the plurality of machine accessible instructions.

6

6. The method as defined in claim 5 , further comprising generating profiling information associated with the simulated execution of the plurality of machine accessible instructions.

7

7. The method as defined in claim 6 , further comprising generating the branch data from the profiling information.

8

8. The method as defined in claim 1 , further comprising generating a set comprising a plurality of edges, wherein each edge of the plurality of edges is associated with a first source basic block and a first destination basic block and wherein the first source basic block is the same as a second source basic block of a second edge within the set or the first destination basic block is the same basic block as a second destination basic block of a third edge.

9

9. The method as defined in claim 1 , wherein generating the set of partial layouts from the plurality of basic blocks comprises inserting a basic block associated with the plurality of basic blocks into the particular partial layout.

10

10. The method as defined in claim 1 , further comprising: calculating a cost associated with the cost metric; identifying a least cost partial layout associated with a plurality of partial layouts; and inserting the least cost partial layout into the substantial layout.

11

11. The method as defined in claim 1 , wherein the cost metric comprises at least one of a first cost associated with incorrectly predicting execution of a first branch and not taking the first branch and a second cost associated with correctly predicting execution of a second branch and not taking the second branch.

12

12. The method as defined in claim 1 , wherein the cost metric comprises at least one of a first cost associated with incorrectly predicting execution of a first branch and taking the first branch and a second cost associated with correctly predicting execution of a second branch and taking the second branch.

13

13. The method as defined in claim 1 , wherein the cost metric comprises a cost associated with unconditionally taking a branch.

14

14. The method as defined in claim 1 , further comprising inserting a branch predictor indicator into the particular partial layout.

15

15. An apparatus comprising: a memory; and a processor coupled to the memory and configured to: identify branch data associated with a plurality of machine accessible instructions; identify a plurality of basic blocks associated with the branch data; search for a set of edges comprising a subset of the plurality of basic blocks, wherein each edge in the set of edges obtained by the search shares either a source basic block or a destination basic block with another edge in the set of edges; generate a set of partial layouts from the subset of the plurality of basic blocks included in the set of edges; generate a substantial layout using a particular partial layout selected from the set of partial layouts based on a cost metric comprising an accumulation of individual costs determined for each pair of adjacent basic blocks in a particular sequential ordering of the plurality of basic blocks included in the particular partial layout, wherein the individual cost for each pair of adjacent basic blocks is determined using a first cost metric when the pair of adjacent basic blocks is connected in the particular partial layout and a second cost metric when the pair of adjacent basic blocks is not connected in the particular partial layout; and determine a plurality of modified machine accessible instructions based on the substantial layout.

16

16. The apparatus as defined in claim 15 , wherein the processor is configured to identify the plurality of basic blocks associated with the branch data by identifying a plurality of equivalence classes associated with the branch data.

17

17. The apparatus as defined in claim 15 , wherein the processor is programmed to: identify a first edge associated with a first source basic block associated with the plurality of basic blocks; and identify a second edge associated with a second source basic block associated with the plurality of basic blocks.

18

18. The apparatus as defined in claim 15 , wherein the processor is programmed to: identify a first edge associated with a first destination basic block associated with the plurality of basic blocks; and identify a second edge associated with a second destination basic block associated with the plurality of basic blocks.

19

19. The apparatus as defined in claim 15 , wherein the processor is programmed to: calculate a cost associated with the cost metric; identify a least cost partial layout associated with a plurality of partial layouts; and insert the least cost partial layout into the substantial layout.

20

20. The apparatus as defined in claim 15 , wherein the cost metric comprises at least one of a first cost associated with incorrectly predicting execution of a first branch and not taking the first branch and a second cost associated with correctly predicting execution of a second branch and not taking the second branch.

21

21. The apparatus as defined in claim 15 , wherein the cost metric comprises at least one of a first cost associated with incorrectly predicting execution of a first branch and taking the first branch and a second cost associated with correctly predicting execution of a second branch and taking the second branch.

22

22. A machine readable medium having instructions stored thereon that, when executed, cause a machine to: identify branch data associated with a plurality of machine accessible instructions; identify a plurality of basic blocks associated with the branch data; search for a set of edges comprising a subset of the plurality of basic blocks, wherein each edge in the set of edges obtained by the search shares either a source basic block or a destination basic block with another edge in the set of edges; generate a partial layout from the subset of the plurality of basic blocks included in the set of edges; generate a substantial layout from the partial layout based on a cost metric comprising an accumulation of individual costs determined for each pair of adjacent basic blocks in a particular sequential ordering of the plurality of basic blocks included in the partial layout, wherein the individual cost for each pair of adjacent basic blocks is determined using a first cost metric when the pair of adjacent basic blocks is connected in the partial layout and a second cost metric when the pair of adjacent basic blocks is not connected in the partial layout; and determine a plurality of modified machine accessible instructions based on the substantial layout.

23

23. The machine readable medium as defined in claim 22 , wherein each particular pair of adjacent blocks comprises a first basic block and a second basic block, and wherein the instructions, when executed, cause the machine to: determine the first cost metric to be a minimum of a first cost combination and a second cost combination, wherein the first cost combination comprises combining a first cost and a second cost, wherein the first cost is associated with taking a first branch between the first basic block and the second basic block but incorrectly predicting execution of a second branch between the first basic block and a third basic block in the partial layout, and the second cost is associated with taking the second branch upon correctly predicting execution of the second branch, and wherein the second cost combination comprises combining a third cost and a fourth cost, wherein the third cost is associated with taking the first branch upon correctly predicting the second branch would not be executed, and the fourth cost is associated with taking the second branch but incorrectly predicting the second branch would not be executed; and determine the second cost metric to be a minimum of a third cost combination, a fourth cost combination, a fifth cost combination and a sixth cost combination, wherein the third cost combination comprises combining a fifth cost and a sixth cost, wherein the fifth cost is associated with taking a third branch between the first basic block and a fourth basic block in the partial layout but incorrectly predicting execution of the second branch between the first basic block and the third basic block, and the sixth cost is associated with taking the second branch upon correctly predicting execution of the second branch, wherein the fourth combination comprises a seventh cost and an eighth cost, wherein the seventh cost is associated with taking the third branch upon correctly predicting the second branch would not be executed, and the eighth cost is associated with taking the second branch but incorrectly predicting the second branch would not be executed, wherein the fifth combination comprises a ninth cost and a tenth cost, wherein the ninth cost is associated with taking the second branch but incorrectly predicting execution of the third branch, and the tenth cost is associated with taking the third branch upon correctly predicting execution of the third branch, and wherein the sixth combination comprises an eleventh cost and a twelfth cost, wherein the eleventh cost is associated with taking the second branch upon correctly predicting the third branch would not be executed, and the twelfth cost is associated with taking the third branch but incorrectly predicting the third branch would not be executed.

24

24. The machine readable medium as defined in claim 22 , wherein the instructions, when executed, cause the machine to: identify a first edge associated with a first source basic block associated with the plurality of basic blocks; and identify a second edge associated with a second source basic block associated with the plurality of basic blocks.

25

25. The machine readable medium as defined in claim 22 , wherein the instructions, when executed, cause the machine to: identify a first edge associated with a first destination basic block associated with the plurality of basic blocks; and identify a second edge associated with a second destination basic block associated with the plurality of basic blocks.

26

26. The machine readable medium as defined in claim 22 , wherein the instructions, when executed, cause the machine to: calculate a cost associated with the cost metric; identify a least cost partial layout associated with a plurality of partial layouts; and insert the least cost partial layout into the substantial layout.

27

27. The machine readable medium as defined in claim 22 , wherein the cost metric comprises at least one of a first cost associated with incorrectly predicting execution of a first branch and not taking the first branch and a second cost associated with correctly predicting execution of a second branch and not taking the second branch.

28

28. The machine readable medium as defined in claim 22 , wherein the cost metric comprises at least one of a first cost associated with incorrectly predicting execution of a first branch and taking the first branch and a second cost associated with correctly predicting execution of a second branch and taking the second branch.

Patent Metadata

Filing Date

Unknown

Publication Date

June 29, 2010

Inventors

Ramesh Peri
Zino Benaissa
Srinivas Doddapaneni

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