Communication System for Connecting Synchronous Devices That Are Uncorrelated in Time

1. A communication system, comprising: a first device including a transmitter with a transmitting terminal; a second device that is not timing correlated with the first device, the second device including a receiver with a receiving terminal; and a transmitting channel coupled between the transmitting and receiving terminals, wherein said receiver comprises: an asynchronous input stage suitable for receiving on said receiving terminal a datum; and a synchronous output stage suitable for outputting said datum, synchronized with a clock signal, on a synchronized receiving terminal.

2. A communication system according to claim 1 , wherein said receiver further comprises a feedback block coupled between said synchronized receiving terminal and a feedback node, in turn coupled to said asynchronous input stage.

3. A communication system according to claim 2 , wherein said asynchronous input stage of said receiver comprises first and second high impedance and feedback stages having respective control terminals coupled to said feedback node, said first high impedance and feedback stage being coupled between a first voltage reference and said receiving terminal, and said second high impedance and feedback stage being coupled between said receiving terminal and a second voltage reference, said high impedance and feedback stages being suitable for holding a correct voltage value at said receiving terminal by supplying said receiving terminal with suitable under-threshold currents.

4. A communication system according to claim 3 , wherein said synchronous output stage of said receiver comprises first and second latches having respective first input terminals connected to said receiving terminal, respective second input terminals configured to receive a negated value of a clock signal and said clock signal, respectively, and respective output terminals connected to each other and to said synchronized receiving terminal, so that when one of the latches is under evaluation, the other of the latches is disabled, avoiding any electric conflict on said synchronized receiving terminal where said datum, synchronized with said clock signal, is present.

5. A communication system according to claim 4 , wherein said first and second latches are almost-tspc latches.

6. A communication system according to claim 3 , wherein said first and second high impedance and feedback stages are symmetrical to each other, the first high impedance and feedback stage including first and second transistors coupled in series with each other, the second high impedance and feedback stage including third and fourth transistors coupled in series with each other and coupled in series with the first and second transistors between said first and second voltage references and said receiving terminal.

7. A communication system according to claim 6 , wherein said second and third transistors are MOS transistors having high leakage currents and said first and fourth transistors are MOS transistors having low leakage currents.

8. A communication system according to claim 6 , wherein said second and third transistors are directly connected to said receiving terminal and are reverse biased, the second transistor having control and bulk terminals coupled to said first voltage reference and the third transistor having control and bulk terminals coupled to said second voltage reference, allowing to store said datum at said receiving terminal under high impedance conditions, thanks to leakage currents passing through the second and third transistors.

9. A communication system according to claim 7 , wherein said first and fourth transistors have respective control terminals realizing said first and second control terminals coupled to said feedback node.

10. A communication system according to claim 9 , wherein: said synchronous output stage of said receiver comprises first and second latches having respective first input terminals connected to said receiving terminals, respective second input terminals receiving a negated value of a clock signal and said clock signal, respectively, and respective output terminals connected to each other and to said synchronized receiving terminal, so that when one of the latches is under evaluation, the other of the latches is disabled, avoiding any electric conflict on said synchronized receiving terminal where said datum being synchronized with said clock signal is present, said first latch includes: fifth, sixth, and seventh transistors coupled in series with each other between said first and second voltage references, said fifth and sixth transistors being interconnected in correspondence with a first inner circuit node and having respective control terminals coupled to each other and to a negated clock signal terminal, said seventh transistor having a control terminal coupled to said receiving terminal; and eighth, ninth, and tenth transistors coupled in series with each other between said first and second voltage references, said eighth and ninth transistors being interconnected in correspondence with said synchronized receiving terminal, said eighth and tenth transistors having respective control terminals connected to each other and to said first inner circuit node, said ninth transistor having a control terminal coupled to said negated clock signal terminal; and said second latch includes: eleventh, twelfth, and thirteenth transistors coupled in series with each other between said first and second voltage references, said eleventh and twelfth transistors being interconnected in correspondence with a second inner circuit node and having respective control terminals coupled to each other and to a clock signal terminal, said thirteenth transistor having a control terminal coupled to said receiving terminal; and fourteenth, fifteenth, and sixteenth transistors coupled in series with each other between said first and second voltage references, said fourteenth and fifteenth transistors being interconnected in correspondence with said synchronized receiving terminal, said fourteenth and sixteenth transistors having respective control terminals connected to each other and to said second inner circuit node, said fifteenth transistor having a control terminal coupled to said clock signal terminal.

11. A communication system according to claim 1 , wherein said feedback block is formed by a CMOS logic inverter realized by a pair of transistors coupled, in series with each other, between first and second voltage references, interconnected in correspondence with said feedback node and having respective control terminals connected to each other and to said synchronized receiving terminal.

12. A communication system according to claim 1 , further comprising an enable block coupled between said receiving terminal and a voltage reference and configured to receive a reset signal.

13. A communication system according to claim 12 , wherein said enable block comprises an enable transistor having a control terminal configured to receive said reset signal.

14. A communication system according to claim 1 , wherein said transmitter is a charge pump transmitter suitable for compensating signal degradations caused by capacitive partitions which characterize the communication system.

15. A communication system according to claim 14 , wherein said charge pump transmitter comprises a charge pump capacitor suitable for injecting additional charge into said transmitting terminal.

16. A communication system according to claim 15 , wherein said charge pump transmitter comprises a driving section and a switching section interconnected by said charge pump capacitor.

17. A communication system according to claim 16 , wherein said driving section of said charge pump transmitter comprises: a NAND gate having respective input terminals coupled to a first and a second input terminal receiving said datum and said clock signal, respectively, as well as an output terminal connected to a first output terminal, suitable for supplying a first driving signal to said switching section; and a logic inverter having an input terminal connected to a third input terminal and receiving said datum and an output terminal connected to a second output terminal, suitable for supplying a second driving signal to the switching section.

18. A communication system according to claim 17 , wherein said switching section of said charge pump transmitter comprises first and second switches coupled in series with each other between first and second voltage references, interconnected in correspondence with said transmitting terminal and having respective control terminals connected to said first and second output terminals of said driving section and configured to receive therefrom said first and second driving signals.

19. A communication system according to claim 1 , wherein: the first and second devices are bidirectional; the transmitter of the first device is coupled between a first input terminal and a first interconnection terminal coupled to the transmitting channel, and has first enable terminal configured to receive a first driving signal; the second device includes a transmitter coupled between a second input terminal and a second interconnection terminal coupled to the transmitting channel, and has a second enable terminal configured to receive a second driving signal; the first device includes a receiver structured to transmit data in a synchronized way with respect to a clock signal; and the first device includes a first pass-gate transistor coupled between the first interconnection terminal and the receiving terminal of the receiver of the first device.

20. A communication system according to claim 19 , wherein said transmitter of the first device is a tri-state buffer configured to be driven by said first driving signal so as to ensure a high impedance condition on said first interconnection terminal when in reception mode.

21. A communication system according to claim 20 , wherein said first pass-gate transistor has a control terminal configured to receive said first driving signal so as to disconnect said receiver of the first device under transmission conditions.

22. A communication system according to claim 21 , wherein the first device includes a reset block configured to receive said first driving signal and said clock signal and supply a reset signal to said receiver of the first device.

23. A method comprising: receiving at a transmitter a datum in the form of a voltage signal; transmitting said datum by said transmitter on a transmitting channel; receiving said datum through said transmitting channel on a receiving terminal of a receiver, the receiving including receiving said datum while high impedance biasing said receiving terminal; producing a synchronized datum by synchronizing said received datum with a clock signal; and outputting said synchronized datum on a synchronized receiving terminal of said receiver.

24. A method according to claim 23 , wherein said high impedance biasing of said receiving terminal includes: enabling a first high impedance stage, coupled to a first voltage reference, using a feedback signal fed back from said synchronized receiving terminal; and disabling a second high impedance stage, coupled to a second voltage reference, using the feedback signal.

25. A method according to claim 24 , wherein synchronizing said datum comprises storing said datum in suitable latches controlled by a negated value of said clock signal and said clock signal, respectively, said latches being coupled between said receiving terminal and said synchronized receiving terminal of said receiver.

26. A device for communicating via a transmitting channel with another device that is not timing correlated with the device, comprising: a receiver that includes: a receiving terminal; an asynchronous input stage suitable for receiving on said receiving terminal a datum; and a synchronous output stage suitable for outputting said datum, synchronized with a clock signal, on a synchronized receiving terminal.

27. A device according to claim 26 , wherein said asynchronous input stage comprises first and second high impedance stages having respective control terminals coupled to said synchronized receiving terminal, said first high impedance stage being coupled between a first voltage reference and said receiving terminal, and said second high impedance and feedback stage being coupled between said receiving terminal and a second voltage reference, said high impedance stages being suitable for holding a correct voltage value at said receiving terminal by supplying said receiving terminal with suitable under-threshold currents.

28. A device according to claim 27 , wherein said first high impedance and feedback stage includes first and second transistors coupled in series with each other between a first voltage reference and the receiving terminal and said second high impedance stage includes third and fourth transistors coupled in series with each other between a second voltage references and said receiving terminal.

29. A device according to claim 28 , wherein said second and third transistors are MOS transistors having high leakage currents and said first and fourth transistors are MOS transistors having low leakage currents.

30. A device according to claim 26 , wherein said synchronous output stage comprises first and second latches having respective first input terminals coupled to said receiving terminal, respective second input terminals configured to receive a negated value of a clock signal and said clock signal, respectively, and respective output terminals coupled to each other and to said synchronized receiving terminal, so that when one of the latches is under evaluation, the other of the latches is disabled, avoiding any electric conflict on said synchronized receiving terminal where said datum, synchronized with said clock signal, is present.

31. A device according to claim 26 , further comprising a transmitter configured to transmit data to the other device via the transmitting channel.