Adaptive Execution Frequency Control Method for Enhanced Instruction Throughput

1. In an instruction processor which processes program instructions, a method comprising: determining when a pre-determined number of first-type instructions are scheduled to be executed, wherein the pre-determined number of first-type instructions is greater than one (1); and when the pre-determined number of first type instructions are scheduled to be executed, automatically switching an execution frequency of the instruction processor from a first frequency that is optimal for processing other-type instructions to a second, pre-established lower frequency, which is optimal for processing the first-type instructions, to enable more efficient execution and higher execution throughput of the pre-determined number of first-type operations, wherein the other-type instructions are less than the pre-determined number of first-type instructions and executed at the first frequency.

2. The method of claim 1 , further comprising automatically switching back from the second, lower frequency to the first frequency when the number of first-type operations has completed execution.

3. The method of claim 2 , wherein the evaluating is completed via a software compiler, which monitors the sequence of instructions within the program instructions during program compilation and issues an interrupt to effect a change in the processor execution frequency to the second frequency when the number of first-type instructions exceeds a threshold number, indicating execution of a slower program.

4. The method of claim 2 , wherein the evaluating is completed via a hardware logic, which monitors the sequence of instructions within the program instructions during instruction scheduling at the processor and issues an interrupt to effect a change in the processor execution frequency to the second frequency when the number of first-type instructions issued for scheduling exceeds a threshold number, indicating execution of a slower program.

5. The method of claim 1 , wherein said determining further comprises: evaluating when a pre-defined threshold number of the first-type instructions are scheduled for execution within executing program code; and when the number of first-type instructions scheduled for execution is at least as great as the threshold number of first-type instructions, triggering the processor to switch the execution frequency to the second, lower execution frequency.

6. The method of claim 5 , wherein the triggering the processor to switch the execution frequency includes switching the processor execution frequency to the second execution frequency after the processor completes execution of previously scheduled other-type instructions.

7. The method of claim 1 , wherein the evaluating comprises: counting the number of first-type instructions being issued to an execution scheduler of the processor; comparing the number of first-type instructions to the pre-set threshold number; automatically issuing an interrupt signal to effect a change of frequency at the processor to the second frequency to enable a higher instruction throughput for the first-type instructions.

8. The method of claim 7 , wherein said automatically issuing comprises forwarding the interrupt signal to a clock and power management (CPM) unit associated with the processor, wherein the CPM unit sets and updates the processor execution frequency based when the interrupt signal is received.

9. The method of claim 1 further comprising: storing a threshold value as a lower limit on a number of consecutive first-type operations in a given interval to trigger the automatic switching of the processor frequency; and wherein said determining comprises comparing the number of first-type operations against the threshold value, such that the automatic switching is activated when the number of first-type operations within the interval is at least the threshold value.

10. The method of claim 1 , wherein: the other-type instructions are instructions which execute at the first optimal frequency that provides maximum processor instruction throughput; and the first-type instructions are arithmetic and logical operations, including multiply operations, which cause the processor to execute at an effective frequency that is less than the second frequency when the processor is set to operate at the first optimal frequency, such that processor instruction throughput is substantially reduced.

11. A data processing system comprising: a processor for processing program instructions; an instruction fetch mechanism within the processor for fetching a sequence of instructions for execution within the processor; and processing logic associated with the processor for: determining when a pre-determined minimum number of first-type instructions are scheduled to be executed, wherein the pre-determined number is greater than one (1); when the pre-determined minimum number of first-type instructions are scheduled to be executed, automatically switching an execution frequency of the instruction processor from a first frequency that is optimal for processing other-type instructions to a second, pre-established lower frequency, which is optimal for processing the first-type instructions, to enable more efficient execution and higher execution throughput of the number of first-type operations, wherein the other-type instructions are less than the pre-determined number of first-type instructions and executed at the first frequency; automatically switching back from the second, lower frequency to the first frequency when the number of first-type operations has completed execution.

12. The data processing system of claim 11 , wherein said logic for determining further comprises logic for: evaluating when a pre-defined threshold number of the first-type instructions are scheduled for execution within executing program code; and when the number of first-type instructions scheduled for execution is at least as great as the threshold number of first-type instructions, triggering the processor to switch the execution frequency to the second, lower execution frequency; wherein the triggering the processor to switch the execution frequency includes switching the processor execution frequency to the second execution frequency after the processor completes execution of previously scheduled other-type instructions.

13. The data processing system of claim 11 , wherein the logic for evaluating comprises logic for: counting the number of first-type instructions being issued to an execution scheduler of the processor; comparing the number of first-type instructions to the pre-set threshold number; and automatically issuing an interrupt signal to effect a change of frequency at the processor to the second frequency to enable a higher instruction throughput for the first-type instructions; wherein said automatically issuing comprises forwarding the interrupt signal to a clock and power management (CPM) unit associated with the processor, wherein the CPM unit sets and updates the processor execution frequency based when the interrupt signal is received.

14. The data processing system of claim 12 , wherein the logic for evaluating is completed via one of: a software compiler, which monitors the sequence of instructions within the program instructions during program compilation and issues an interrupt to effect a change in the processor execution frequency to the second frequency when the number of first-type instructions exceeds a threshold number, indicating execution of a slower program; and a hardware logic, which monitors the sequence of instructions within the program instructions during instruction scheduling at the processor and issues an interrupt to effect a change in the processor execution frequency to the second frequency when the number of first-type instructions issued for scheduling exceeds a threshold number, indicating execution of a slower program.

15. The data processing system of claim 11 , further comprising logic for: storing a threshold value as a lower limit on a number of consecutive first-type operations in a given interval to trigger the automatic switching of the processor frequency; and wherein said determining comprises comparing the number of first-type operations against the threshold value, such that the automatic switching is activated when the number of first-type operations within the interval is at least the threshold value.

16. The data processing system of claim 11 , wherein: the other-type instructions are instructions which execute at the first optimal frequency that provides maximum processor instruction throughput; and the first-type instructions are arithmetic and logical operations, including multiply operations, which cause the processor to execute at an effective frequency that is less than the second frequency when the processor is set to operate at the first optimal frequency, such that processor instruction throughput is substantially reduced.

17. A processor comprising: an execution pipeline for executing various types of program instructions including (a) regular-type instructions which execute at a first optimal frequency that provides maximum processor instruction throughput; and (b) a first-type instructions, such as arithmetic and logical operations, including multiply operations, which cause the processor to execute at an effective frequency that is less than a second frequency that is optimal for executing the first-type instructions, when the processor is set to operate at the first optimal frequency, such that processor instruction throughput is substantially reduced; and processing logic associated with the processor for: determining when a pre-determined minimum number of first-type instructions are scheduled to be executed, wherein the pre-determined number is greater than one (1); when the pre-determined minimum number of first-type instructions are scheduled to be executed, automatically switching an execution frequency of the instruction processor from a first frequency that is optimal for processing other-type instructions to a second, pre-established lower frequency, which is optimal for processing the first-type instructions, to enable more efficient execution and higher execution throughput of the number of first-type operations, wherein the other-type instructions are less than the pre-determined number of first-type instructions and executed at the first frequency; and automatically switching back from the second, lower frequency to the first frequency when the number of first-type operations has completed execution.

18. The processor of claim 17 , wherein said logic for determining further comprises logic for: evaluating when a pre-defined threshold number of the first-type instructions are scheduled for execution within executing program code; and when the number of first-type instructions scheduled for execution is at least as great as the threshold number of first-type instructions, triggering the processor to switch the execution frequency to the second, lower execution frequency; wherein the triggering the processor to switch the execution frequency includes switching the processor execution frequency to the second execution frequency after the processor completes execution of previously scheduled other-type instructions.

19. The processor system of claim 17 , wherein the logic for evaluating comprises logic for: storing a threshold value as a lower limit on a number of consecutive first-type operations in a given interval to trigger the automatic switching of the processor frequency; and counting the number of first-type instructions being issued to an execution scheduler of the processor; comparing the number of first-type instructions to the pre-set threshold number, wherein the automatic switching is activated when the number of first-type operations within the interval is at least the threshold value; and automatically issuing an interrupt signal to effect a change of frequency at the processor to the second frequency to enable a higher instruction throughput for the first-type instructions; wherein said automatically issuing comprises forwarding the interrupt signal to a clock and power management (CPM) unit associated with the processor, wherein the CPM unit sets and updates the processor execution frequency based when the interrupt signal is received.

20. The data processing system of claim 18 , wherein the logic for evaluating is completed via one of: a software compiler, which monitors the sequence of instructions within the program instructions during program compilation and issues an interrupt to effect a change in the processor execution frequency to the second frequency when the number of first-type instructions exceeds a threshold number, indicating execution of a slower program; and a hardware logic, which monitors the sequence of instructions within the program instructions during instruction scheduling at the processor and issues an interrupt to effect a change in the processor execution frequency to the second frequency when the number of first-type instructions issued for scheduling exceeds a threshold number, indicating execution of a slower program.