Apparatus and Method of Calibrating On-Die Termination for Semiconductor Integrated Circuit

1. An apparatus for calibrating on-die termination for a semiconductor integrated circuit, the apparatus comprising: an operation control unit that generates an amp enable signal and a final code update signal in response to an on-die termination calibration command; a comparing unit that compares a code conversion voltage with a reference voltage, and outputs a comparison result signal in response to the amp enable signal; a code control unit that compares a current comparison result signal and a previous comparison result signal and outputs an external code update signal in response to the final code update signal; a first counter that changes an internal code in response to the comparison result signal; and a second counter that outputs an external code in response to the external code update signal and the internal code.

2. The apparatus of claim 1 , further comprising: a driver leg that distributes a power supply voltage according to a distribution ratio between resistance selected according to the internal code and external resistance and generates the code conversion voltage.

3. The apparatus of claim 1 , wherein the comparing unit includes an amplifier that operates according to the amp enable signal.

4. The apparatus of claim 1 , wherein the code control unit includes: a comparison circuit that compares the current comparison result signal with the previous comparison result signal to determine whether or not levels thereof are the same; and a determination circuit that determines whether or not to output the external code update signal according to an output signal of the comparison circuit.

5. The apparatus of claim 4 , wherein the comparison circuit latches the previous comparison result signal and compares the previous comparison result signal with the current comparison result signal.

6. The apparatus of claim 5 , wherein the comparison circuit latches the previous comparison result signal until the current comparison result signal is input, according to the amp enable signal.

7. The apparatus of claim 6 , wherein the comparison circuit includes: a flip flop that has a clock terminal receiving the amp enable signal and an input terminal receiving the comparison result signal; and a logic gate that performs an XOR operation on an output signal of the flip flop and the comparison result signal.

8. The apparatus of claim 4 , wherein the determination circuit includes a logic gate that performs an AND operation on the output signal of the comparison circuit and an external code update signal according to each comparison operation performed by the comparing unit.

9. The apparatus of claim 1 , wherein the operation control unit is configured to generate the amp enable signal once for each cycle of calibration operations.

10. The apparatus of claim 1 , wherein the code control unit is configured to output the final code update signal as the external update signal in response to the comparison result signal.

11. The apparatus of claim 1 , wherein the code control unit is configured to prohibit the external code update signal from being enabled when the current comparison result signal and the previous comparison result signal are not the same.