Flash Memory Interface for Disk Drive

1. A method for coupling a disk drive to a host via a disk controller, the method comprising: coupling the disk controller to the host using a NAND flash memory interface having a 14-line bus; interpreting commands received from the host via the NAND flash memory interface using a flash controller; emulating data transfer protocols of the disk drive using the flash controller; storing data received from the host and from the disk drive in a buffer memory; controlling the buffer memory via a buffer manager interface according to data transfer rates of the host and the disk drive; coupling a register memory to the flash controller; coupling the register memory to a processor of the disk controller via a processor bus; storing commands programmed by the processor and the host in the register memory; and synchronizing control signals between the flash controller and the buffer manager interface.

2. The method of claim 1 , wherein emulating data transfer protocols comprises: controlling the NAND flash memory interface for implementing a random read of the disk drive by the host; and controlling the NAND flash memory interface for implementing a random write of the disk drive by the host.

3. The method of claim 1 , wherein emulating data transfer protocols further comprises: controlling the NAND flash memory interface for implementing a sequential read of the disk drive by the host; and controlling the NAND flash memory interface for implementing a sequential write of the disk drive by the host.

4. The method of claim 1 , wherein emulating data transfer protocols further comprises: controlling the NAND flash memory interface for implementing a transfer of commands between the host and the disk drive.

5. The method of claim 4 further comprising: mapping a set of disk drive commands to a corresponding set of flash memory commands.

6. The method of claim 5 , wherein the set of disk drive commands comprises: Read DMA EXT; Write DMA EXT; Standby Immediate; Flush Cache EXT; and Reset.

7. The method of claim 1 further comprising: coupling the flash controller to the processor bus through the register memory; and coupling the flash controller to a buffer manager of the disk drive through a memory wrapper, wherein the memory wrapper transfers data to and from the buffer manager in a first-in-first-out manner.

8. The method of claim 1 , wherein controlling the buffer memory comprises: storing read data from the disk drive in the buffer memory to compensate for differences in data transfer rates between the host and the disk drive; and sending a data ready signal to the host to indicate there is data in the buffer memory.

9. The method of claim 1 , wherein controlling the buffer memory further comprises: storing write data from the host in the buffer memory to compensate for differences in data transfer rates between the host and the disk drive; and sending a data ready signal to the host to indicate there is space in the buffer memory.

10. A disk controller for coupling a disk drive to a host, the disk controller comprising: an interface controller to interface the disk drive to the host using a NAND flash memory interface having a 14-line bus; and a buffer memory to store data received from the host and from the disk drive; wherein the interface controller comprises: a flash controller to interpret commands received from the host via the NAND flash memory interface and to emulate data transfer protocols of the disk drive; a memory wrapper in communication with the flash controller, wherein the memory wrapper controls the buffer memory via a buffer manager interface according to data transfer rates of the host and the disk drive; a register memory in communication with the flash controller and in communication with a processor of the disk controller via a processor bus, wherein the register memory stores commands programmed by the processor and the host; and a synchronizing module that synchronizes control signals between the flash controller and the buffer manager interface.

11. The disk controller of claim 10 , wherein the flash controller: controls the NAND flash memory interface to implement a random read of the disk drive; and controls the NAND flash memory interface to implement a random write of the disk drive.

12. The disk controller of claim 10 , wherein the flash controller: controls the NAND flash memory interface to implement a sequential read of the disk drive; and controls the NAND flash memory interface to implement a sequential write of the disk drive.

13. The disk controller of claim 10 , wherein the flash controller: controls the NAND flash memory interface to implement a transfer of commands between the host and the disk drive.

14. The disk controller of claim 13 , wherein the flash controller: maps a set of disk drive commands to a corresponding set of flash memory commands.

15. The disk controller of claim 14 , wherein the set of disk drive commands comprises: Read DMA EXT; Write DMA EXT; Standby Immediate; Flush Cache EXT; and Reset.

16. The disk controller of claim 10 , wherein the flash controller: stores read data from the disk drive in the buffer memory to compensate for differences in data transfer rates between the host and the disk drive; and sends a data ready signal to the host to indicate there is data in the buffer memory.

17. The disk controller of claim 10 , wherein the flash controller: stores write data from the host in the buffer memory to compensate for differences in data transfer rates between the host and the disk drive; and sends a data ready signal to the host to indicate there is space in the buffer memory.

18. The disk controller of claim 10 , wherein the processor is implemented by an embedded processor or by an external microprocessor.

19. The disk controller of claim 10 , wherein the 14-line bus is a 14-line parallel bus that includes 8 bidirectional input/output (I/O) data lines and 6 control lines, and wherein the 6 control lines consist of command latch enable (CLE), address latch enable (ALE), chip enable (CE), read enable (RE), write enable (WE), and ready/busy (R/B).

20. The disk controller of claim 10 , wherein the disk drive is embedded in at least one of a portable computer and a consumer electronics device comprising the host.

21. A system for coupling a disk drive to a host via a disk controller, the system comprising: first interfacing means for interfacing the disk drive to the host using a NAND flash memory interface having a 14-line bus; and first storing means for storing data received from the host and from the disk drive; wherein the first interfacing means comprises: emulating means for interpreting commands received from the host via the NAND flash memory interface and for emulating data transfer protocols of the disk drive; first controlling means for controlling the first storing means via second interfacing means for interfacing a buffer manager according to data transfer rates of the host and the disk drive; second storing means for storing commands programmed by a processor of the disk controller and the host, wherein the second storing means is in communication with the emulating means and is in communication with the processor via a processor bus; and synchronizing means for synchronizing control signals between the emulating means and the second interfacing means.

22. The system of claim 21 , wherein the emulating means comprise: second controlling means for controlling the NAND flash memory interface to implement a random read of the disk drive; and third controlling means for controlling the NAND flash memory interface to implement a random write of the disk drive.

23. The system of claim 21 , wherein the emulating means comprise: second controlling means for controlling the NAND flash memory interface to implement a sequential read of the disk drive; and third controlling means for controlling the NAND flash memory interface to implement a sequential write of the disk drive.

24. The system of claim 21 , wherein the emulating means comprise: second controlling means for controlling the NAND flash memory interface to implement a transfer of commands between the host and the disk drive.

25. The system of claim 24 further comprising: mapping means for mapping a set of disk drive commands to a corresponding set of flash memory commands.

26. The system of claim 21 further comprising: first coupling means for coupling the emulating means to the processor bus through the second storing means; and second coupling means for coupling to the buffer manager of the disk drive through a memory wrapper, wherein the memory wrapper transfers data to and from the buffer manager in a first-in-first-out manner.

27. The system of claim 21 , wherein the first controlling means comprise: third storing means for storing read data from the disk drive in the first storing means to compensate for differences in data transfer rates between the host and the disk drive; and sending means for sending a data ready signal to the host to indicate there is data in the first storing means.

28. The system of claim 21 , wherein the first controlling means comprise: third storing means for storing write data from the host in the first storing means to compensate for differences in data transfer rates between the host and the disk drive; and sending means for sending a data ready signal to the host to indicate there is space in the first storing means.

29. A disk controller for interfacing a disk drive to a host, the disk controller comprising: a flash register that communicates with a processor of the disk controller via an advanced high-speed bus (AHB) of the disk controller, and stores control commands programmed by the processor and the host; a flash controller that communicates with the host using a 14-line bus of a NAND flash memory interface, emulates data transfer protocols of the disk drive, decodes flash commands received from the host via the NAND flash memory interface using a flash state machine, and generates control signals for the disk controller to control the disk drive; a FIFO wrapper that controls data transfers to and from a buffer manager of the disk controller via a buffer manager interface according to data transfer rates of the host and the disk drive in response to the flash commands, wherein a direction of the data transfers is controlled by the control commands stored in the flash register; and a synchronization module that synchronizes timing signals between the flash controller and the buffer manager interface.

30. The disk controller of claim 29 further comprising a defect management module that: communicates with the processor via the AHB, communicates with the buffer manager, and performs track format generation and defect management of the disk drive based on the flash commands.

31. The disk controller of claim 29 , wherein the disk controller is implemented in an integrated circuit (IC).