Prediction of Data Values Read from Memory by a Microprocessor Using the Storage Destination of a Load Operation

1. A method for predicting a data value that will result from a load operation to be executed by a microprocessor, the method comprising: obtaining an address and branch history values of a new instruction from a program counter; accessing an entry in a load value prediction table using a key created based on the address and the branch history values of the new instruction to retrieve a predicted data value, prior to determining whether the new instruction comprises the load operation; storing the predicted data value in a physical storage destination of the microprocessor prior to determining whether the new instruction comprises the load operation, wherein the storage destination is a destination for a loaded data value resulting from executing the load operation, upon determining that the new instruction comprises the load operation, executing the new instruction using the predicted data value stored in the physical storage destination; wherein register renaming is used to provide a second physical register that stores one or more values that were stored in the storage destination prior to storing the predicted data value, and if a misprediction is determined to have occurred, the method further comprises checking a bit associated with the storage destination in which the predicted data value was stored to determine whether or not the predicted data value has already been used by one or more subsequent operations to the load operation to determine whether the subsequent operations are to be rolled back.

2. The method of claim 1 wherein the storage destination is a register of the microprocessor.

3. The method of claim 2 wherein the register is provided in a register file of the microprocessor.

4. The method of claim 2 wherein the register is a renamed register.

5. The method of claim 1 wherein the loaded data value is stored in place of the predicted data value in the storage destination.

6. The method of claim 1 further comprising executing the load operation and comparing the predicted data value with the loaded data value resulting from executing the load operation, wherein if the predicted and loaded data values are different then a misprediction has occurred.

7. The method of claim 6 wherein register renaming is used to provide a second physical register that stores one or more values that were stored in the register prior to storing the predicted data value.

8. The method of claim 1 further comprising using the predicted data value in speculative execution of one or more subsequent operations to the load operation.

9. The method of claim 1 further comprising storing control information for a replacement entry in the physical storage destination if an entry in the table corresponding to the load operation is not found.

10. The method of claim 1 further comprising replacing the predicted data value in the entry in the load value prediction table with the loaded data value, when the loaded data value is determined to be more likely than the predicted data value to yield a correct predicted data value result for future load operations.

11. A microprocessor operative to predict a data value that will result from a load operation to be executed by the microprocessor, the microprocessor comprising: an instruction fetcher configured to obtain an address and branch history values of a new instruction from a program counter; a mechanism operative to access an entry in a load value prediction table using a key created based on the address and the branch history values of the new instruction to retrieve a predicted data value, prior to determining whether the new instruction comprises the load operation; a mechanism operative to store the predicted data value in a physical storage destination of the microprocessor prior to determining whether the new instruction comprises the load operation, wherein the storage destination is a destination for a loaded data value resulting from executing the load operation; a mechanism operative to execute, upon determining that the new instruction comprises the load operation, the new instruction using the predicted data value stored in the physical storage destination; a second physical register provided using register renaming, the second physical register storing one or more values that were stored in the storage destination prior to storing the predicting data value, and a mechanism operative to check, if a misprediction is determined to have occurred, a bit associated with the storage destination in which the predicted data value was stored to determine whether or not the predicted data value has already been used by one or more subsequent operations to the load operation to determine whether the subsequent operations are to be rolled back.

12. The microprocessor of claim 11 wherein the storage destination is a register of the microprocessor.

13. The microprocessor of claim 12 wherein the register is a renamed register.

14. The microprocessor of claim 11 wherein the loaded data value is stored in place of the predicted data value in the storage destination.

15. The microprocessor of claim 11 further comprising a mechanism operative to execute the load operation; and a mechanism operative to compare the predicted data value with the loaded data value resulting from executing the load operation, wherein if the predicted and loaded data values are different then a misprediction has occurred.

16. The microprocessor of claim 15 further comprising a mechanism operative to use the predicted data value in speculative execution of one or more subsequent operations to the load operation.

17. The microprocessor of claim 16 further comprising a second physical register provided using register renaming, the second physical register storing one or more values that were stored in the storage destination prior to storing the predicted data value, and wherein the one or more values are accessed if a misprediction has occurred and the speculative execution is to be rolled back.

18. The microprocessor of claim 11 further comprising a mechanism operative to store control information for a replacement entry in the physical storage destination if an entry in the table corresponding to the load operation is not found.

19. The microprocessor of claim 11 further comprising a mechanism operative to replace the predicted data value in the entry in the load value prediction table with the loaded data value, when the loaded data value is determined to be more likely than the predicted data value to yield a correct predicted data value result for future load operations.

20. A computer readable storage medium including program instructions to be implemented by a computer and for predicting a data value that will result from a load operation to be executed by the microprocessor, the program instructions for: obtaining an address and branch history values of a new instruction from a program counter; accessing an entry in a load value prediction table using a key created based on the address and the branch history values of the new instruction to retrieve a predicted data value, prior to determining whether the new instruction comprises the load operation; storing the predicted data value in a physical storage destination of the microprocessor prior to determining whether the new instruction comprises the load operation, wherein the storage destination is a destination for a loaded data value resulting from executing the load operation, upon determining that the new instruction comprises the load operation, executing the new instruction using the predicted data value stored in the physical storage destination; wherein register renaming is used to provide a second physical register that stores one or more values that were stored in the storage destination prior to storing the predicted data value, and if a misprediction is determined to have occurred, checking a bit associated with the storage destination in which the predicted data value was stored to determine whether or not the predicted data value has already been used by one or more subsequent operations to the load operation to determine whether the subsequent operations are to be rolled back.

21. A microprocessor operative to predict a data value that will result from a load operation to be executed by the microprocessor, the microprocessor comprising: means for obtaining an address and branch history values of a new instruction from a program counter; means for accessing an entry in a load value prediction table using a key created based on the address and the branch history values of the new instruction to retrieve, prior to determining whether the new instruction comprises the load operation; means for storing the predicted data value in a physical storage destination of the microprocessor prior to determining whether the new instruction comprises the load operation, wherein the storage destination is a destination for a loaded data value resulting from executing the load operation, means for executing, upon determining that the new instruction comprises the load operation, the new instruction using the predicted data value stored in the physical storage destination, wherein register renaming is used to provide a second physical register that stores one or more values that were stored in the storage destination prior to storing the predicted data value, and means for checking, if a misprediction is determined to have occurred, a bit associated with the storage destination in which the predicted data value was stored to determine whether or not the predicted data value has already been used by one or more subsequent operations to the load operation to determine whether the subsequent operations are to be rolled back.