Legal claims defining the scope of protection, as filed with the USPTO.
1. A trellis encoding device comprising: a trellis encoder block that comprises a plurality of memories, and outputs a bit value determined by a state of the memories; a Reed-Solomon re-encoder that receives the bit value output from the trellis encoder block, and generates a parity corresponding to the bit value; and an adder that receives the parity generated by the Reed-Solomon re-encoder and a transmission stream comprising a parity, and corrects the parity of the transmission stream by adding the parity generated by the Reed-Solomon re-encoder to the transmission stream, thereby generating a parity-corrected transmission stream.
2. The trellis encoding device of claim 1 , further comprising a multiplexer that receives the parity-corrected transmission stream generated by the adder, and outputs the parity-corrected transmission stream to the trellis encoder block; wherein the trellis encoder block trellis-encodes the parity-corrected transmission stream output from the multiplexer, thereby generating a trellis-encoded transmission stream.
3. The trellis encoding device of claim 2 , further comprising a map that receives the trellis-encoded transmission stream generated by the trellis encoder block, maps the trellis-encoded transmission stream into data symbols, and outputs the data symbols.
4. The trellis encoding device of claim 3 , wherein the data symbols are 8-level data symbols.
5. The trellis encoding device of claim 1 , wherein the trellis encoder block comprises: a plurality of trellis encoders that output trellis-encoded data; a splitter that receives the parity-corrected transmission stream and outputs the parity-corrected transmission stream to the trellis encoders in sequence; and a de-splitter that sequentially outputs the trellis-encoded data output by the trellis encoders.
6. The trellis encoding device of claim 5 , wherein each of the trellis encoders comprises: a first memory that outputs a value stored in the first memory as a first part of the bit value, the first memory being one of the memories of the trellis encoder block; a second memory that outputs a value stored in the second memory as a second part of the bit value, the second memory being one of the memories of the trellis encoder block; and a third memory that outputs a value stored in the third memory to the second memory, the third memory being one of the memories of the trellis encoder block.
7. The trellis encoding device of claim 6 , wherein the bit value output from the trellis encoder block is a combination of the first part of the bit value output from the first memory and the second part of the bit value output from the second memory; and wherein the Reed-Solomon re-encoder generates the parity corresponding to the bit value based on the combination of the first part of the bit value and the second part of the bit value.
8. The trellis encoding device of claim 6 , wherein the transmission stream received by the adder is a transmission stream comprising known data and a normal stream.
9. The trellis encoding device of claim 8 , wherein the transmission stream received by the adder is a dual transmission stream further comprising a turbo stream.
10. The trellis encoding device of claim 8 , wherein the known data has a known pattern used to perform channel equalization in a receiver that receives the transmission stream.
11. The trellis encoding device of claim 8 , wherein the parity-corrected transmission stream comprises the known data; wherein the trellis encoders trellis-encode the known data in the parity-corrected transmission stream; and wherein the trellis encoders trellis-encode the bit value to initialize the first memory, the second memory, and the third memory to a known state immediately before trellis-encoding the known data.
12. The trellis encoding device of claim 1 , wherein the trellis encoder block uses the memories in performing a trellis encoding operation.
13. The trellis encoding device of claim 1 , wherein the trellis encoder block trellis-encodes the bit value to initialize the memories to a zero state.
14. The trellis encoding device of claim 1 , wherein the adder adds the parity generated by the Reed-Solomon re-encoder to the parity of the transmission stream, thereby generating the parity-corrected transmission stream.
15. The trellis encoding device of claim 1 , wherein the Reed-Solomon re-encoder outputs a control signal indicating whether an initialization operation for initializing the memories to a known state is to be performed; wherein the trellis encoding device further comprises a multiplexer that receives the transmission stream received by the adder, the parity-corrected transmission stream from the adder, and the control signal from the Reed-Solomon re-encoder, and outputs a transmission stream to be encoded to the trellis encoder block; wherein the multiplexer outputs the transmission stream to the trellis encoder block as the transmission stream to be encoded when the control signal indicates that the initialization operation is not to be performed, and outputs the parity-corrected transmission stream to the trellis encoder block as the transmission stream to be encoded when the control signal indicates that the initialization operation is to be performed; and wherein the trellis encoder block encodes the transmission stream to be encoded output from the multiplexer.
16. A trellis encoding method for trellis-encoding a transmission stream with a trellis encoder, the trellis encoder comprising a plurality of memories, the transmission stream comprising a parity, the trellis encoding method comprising: generating a bit value determined by a state of the memories of the trellis encoder; generating a parity corresponding to the bit value; and correcting the parity of the transmission stream by adding the parity corresponding to the bit value to the transmission stream, thereby generating a parity-corrected transmission stream.
17. The trellis encoding method of claim 16 , further comprising: inputting the parity-corrected transmission stream to the trellis encoder; trellis-encoding the parity-corrected transmission stream with the trellis encoder to generate a trellis-encoded transmission stream; mapping the trellis-encoded transmission stream into data symbols; and outputting the data symbols.
18. The trellis encoding method of claim 16 , wherein the memories of the trellis encoder comprise: a first memory that outputs a value stored in the first memory as a first part of the bit value; a second memory that outputs a value stored in the second memory as a second part of the bit value; and a third memory that outputs a value stored in the third memory to the second memory; and wherein the generating of the bit value comprises combining the first part of the bit value output from the first memory and the second part of the bit value output from the second memory to generate the bit value.
19. The trellis encoding method of claim 18 , wherein the transmission stream is a transmission stream comprising known data and a normal stream.
20. The trellis encoding method of claim 19 , wherein the transmission stream is a dual transmission stream further comprising a turbo stream.
21. The trellis encoding method of claim 19 , wherein the known data has a known pattern used to perform channel equalization in a receiver that receives the transmission stream.
22. The trellis encoding method of claim 18 , wherein the parity-corrected transmission stream comprises the known data; and wherein the trellis encoding method further comprises: inputting the parity-corrected transmission stream to the trellis encoder; trellis-encoding the parity-corrected transmission stream with the trellis encoder; inputting the bit value to the trellis encoder in place of the parity-corrected transmission stream immediately before trellis-encoding the known data in the parity-corrected transmission stream; trellis-encoding the bit value with the trellis encoder to initialize the first memory, the second memory, and the third memory to a known state; inputting the parity-corrected transmission stream to the trellis encoder in place of the bit value when the first memory, the second memory, and the third memory have been initialized to the known state; and trellis-encoding the known data in the parity-corrected transmission stream with the trellis encoder.
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October 26, 2010
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