Redundant Ethernet Packet Network Management

1. A network node for operation in a redundant network having a plurality of nodes comprising: an Ethernet switch having first and second network ports; first and second processors in communication with the Ethernet switch, the first processor connected to the first network port and the second processor connected to the second network port, the processors being configured to determine whether the network node is a master node from among the plurality of nodes in the network, where determining includes: sending a configuration packet to each node in the network, the configuration packet comprising an identification number representing the node in the network from which the configuration packet originates, where each node in the network has a unique identification number, and; comparing the identification number in configuration packets received by the node to the identification number for the node, where the master node is designated based on the comparison of the value of the identification numbers; and a means for creating a virtual break in the network at one of the network connections if the node determines that it is the master node; wherein each of the first and second processors implements a watchdog timer by executing instructions to: (a) initialize the watchdog timer and clear a watchdog timer bit; (b) monitor the network port for activity within a predetermined period of time, if there is no activity on the network port within the predetermined period of time, set the watchdog bit; (c) continue to monitor the network port for activity thereafter, and (i) if the port becomes active and receives a packet, set a receive packet bit and clear the watchdog bit, or (ii) if no packets are received on the network port, check the watchdog bit and if the watchdog bit is set, clear the receive packet bit.

2. A redundant network system comprising a plurality of the network nodes of claim 1 in digital communication.

3. The network node of claim 1 , wherein the first and second processors are general purpose processors having software for determining whether the network node is a master node from among the plurality of nodes in the network.

4. The network node of claim 1 , wherein the first and second processors are application specific integrated circuits having circuitry for determining whether the network node is a master node from among the plurality of nodes in the network.

5. The network node of claim 1 , wherein the first and second processors are field programmable gate arrays having firmware for determining whether the network node is a master node from among the plurality of nodes in the network.

6. The network node of claim 1 , wherein the node having the highest value identification number is designated as the master node.

7. The network node of claim 1 , wherein the configuration packet comprises a header having a node identification number.

8. The network node of claim 7 , wherein the header includes a control portion.

9. The network node of claim 8 , wherein the control portion includes 8 bits.

10. The network node of claim 8 , wherein the control portion includes a node master bit, the node master bit being set to a master node value by a source node, and being cleared by any host node that would be the master node as a result of the comparison of identification number between the source node and the host node.

11. The network node of claim 10 , wherein when the host node receives a configuration packet having the host node's identification number with the master node value cleared, the host node ensures that it does not provide a virtual break in the network.

12. The network node of claim 10 , wherein when the host node receives a configuration packet having the host node's identification number with the master node value set, the host node acts as a master node and provides a virtual break in the network.

13. The network node of claim 8 , wherein the control portion includes a switch reset bit, and when a new master node is designated, the switch reset bit is set to indicate to nodes receiving the configuration packet that the nodes should be reset.

14. The network node of claim 8 , wherein the control portion includes a reconfigure node bit that is set to indicate that the network is to be reconfigured and a new master node designated.

15. The network node of claim 14 , wherein the reconfigure node bit is set to indicate that the network is to be reconfigured upon start-up of a node.

16. The network node of claim 14 , wherein the reconfigure node bit is set to indicate that the network is to be reconfigured upon an indication from a watchdog timer system.

17. The network node of claim 14 , wherein all packets are configuration packets and the reconfigure node bit is set to indicate that the network is to be reconfigured upon determining that a new master node is designated.

18. The network node of claim 1 , wherein the first processor is connected only to the first network port and the second processor is connected only to the second network port.

19. The network node of claim 18 , wherein the first and second processors are connected by a forwarding bus and the forwarding bus transfers data for another network node from the first network port to the second network port.