Legal claims defining the scope of protection, as filed with the USPTO.
1. A fault location estimation system that is implemented by a data processing device and that estimates fault location in a logic circuit, said system comprising: means that classifies locations with a high fault possibility into groups based on error-observation node information acquired from a test result of the logic circuit and that performs fault simulation for confirming and estimating a plurality of fault locations; output means that outputs single-fault estimation results and multiple-fault estimation results, that is, a number of fault candidate groups corresponding to a number of multiple actual faults, fault candidate groups corresponding to each of actual faults, fault candidates included in a fault candidate group, and a fault type of each fault candidate; single-fault-assumed diagnostic means that narrows fault locations in the logic circuit assuming a single fault by referencing logic circuit configuration information and signal line expected values stored in a logic circuit information storage unit and that stores fault candidates in the logic circuit, types of the faults, and detected error-observation nodes at which an error arrives from the fault candidates, which are a result of narrowing the fault locations, into a single-fault diagnosis result storage unit; error-observation node basis classification means that classifies error propagating fault candidates into groups according to the error-observation nodes using the fault candidates and the error-observation nodes stored in said single-fault diagnosis result storage unit and stores the groups in a fault candidate classification storage unit as fault candidate groups; inclusion fault candidate group selection means that acquires a relation between each fault candidate group and a fault output by referencing the logic circuit configuration information and the fault candidate groups stored in said fault candidate classification storage unit, calculates an inclusion relation among the fault candidate groups, and extracts common candidates; and inter-pattern overlapping means that calculates combinations of the fault candidate groups that can reproduce the test result in all test patterns by referencing the fault candidates in said single-fault diagnosis result storage unit and the fault candidate groups in said fault candidate classification storage unit, stores the calculated combinations in a combination storage unit and, if there are common fault candidates in the calculated fault candidate groups, extracts the common fault candidates and re-registers the common fault candidates in said fault candidate classification storage unit as a new fault candidate group.
2. The fault location estimation system according to claim 1 , further comprising: multiple-fault simulation checking means that references said logic circuit information storage unit, said single-fault diagnosis result storage unit, said fault candidate classification storage unit, and said combination storage unit to reference the logic circuit configuration information, the signal line expected values, the fault candidates, the fault types of the fault candidates, the fault candidate group information, and the combination information on the fault candidate group information, selects fault candidates from the combinations of the fault candidate groups, one from each fault candidate group, and performs multiple-fault simulation assuming a fault based on the fault types of the selected fault candidates, and compares the simulation result with the test result and outputs a combination of the fault candidate groups, which matches relatively well with the test result and has a relatively high fault possibility, as well as the fault types of the fault candidates included in the combination of the fault candidate groups.
3. The fault location estimation system according to claim 1 , comprising: fan-in cone classification means that performs a fan-in trace from error-observation nodes by referencing logical circuit configuration information stored in a logic circuit information storage unit, classifies traced in-circuit nodes into groups according to error-observation nodes, and stores the grouped result in a fault candidate storage unit; in-node-group fault candidate extraction means that extracts signal lines for each node group by referencing the logic circuit configuration information and signal line expected values stored in said logic circuit information storage unit and the node groups related to the error-observation nodes stored in said fault candidate storage unit, performs single-fault simulation assuming a fault by referencing signal line logic states, and stores signal lines, through which a fault propagates to the error-observation nodes related to the node groups, in a fault candidate classification storage unit as fault candidates; inclusion fault candidate group selection means that acquires a relation between each fault candidate group and a fault output by referencing the logic circuit configuration information stored in said logic circuit information storage unit and fault candidate group information stored in said fault candidate classification storage unit, calculates an inclusion relation among the fault candidate groups, and extracts common candidates; and inter-pattern overlapping means that calculates combinations of the fault candidate groups that can reproduce the test result in all test patterns by referencing the fault candidates in said fault candidate storage unit and the fault candidate groups in said fault candidate classification storage unit, stores the calculated combinations in a combination storage unit and, if there are common fault candidates in the calculated fault candidate groups, extracts only the common fault candidates and re-registers the common fault candidates in said fault candidate classification storage unit as a new fault candidate group.
4. The fault location estimation system according to claim 3 , further comprising: multiple-fault simulation checking means that references said logic circuit information storage unit, said fault candidate storage unit, said fault candidate classification storage unit, and said combination storage unit to reference the logic circuit configuration information, the signal line expected values, the fault candidates, the fault types of the fault candidates, the fault candidate group information, and the combination information on the fault candidate group information, selects fault candidates from the combinations of the fault candidate groups, one from each fault candidate group, and performs multiple-fault simulation assuming a fault based on the fault types of the selected fault candidates, compares the simulation result with the test result, and outputs a combination of the fault candidate groups, which matches relatively well with the test result and has a relatively high fault possibility, as well as the fault types of the fault candidates included in the combination of the fault candidate groups.
5. The fault location estimation system according to claim 1 , comprising: single-fault-assumed diagnostic means that assumes a single fault by referencing logic circuit configuration information and signal line expected values stored in a logic circuit information storage unit and that stores fault candidates in the logic circuit, fault types of the fault candidates, and detected error-observation nodes, at which an error arrives from the fault candidates, into a single-fault diagnosis result storage unit; error propagating path extraction means that extracts error propagating paths to an error-observation node through each fault candidate using the logic circuit configuration information and signal line expected values stored in said logic circuit information storage unit and the fault candidates and error-observation nodes stored in said single-fault diagnosis result storage unit and stores the extracted error propagating paths in a fault candidate classification storage unit as error propagating path information; error propagating path classification means that selects a candidate with a relatively high fault possibility considering scores of the fault candidates by referencing the fault candidates stored in said single-fault diagnosis result storage unit and the error propagating path information stored in said fault candidate classification storage unit, classifies error propagating paths, related to an error propagating path through which the selected fault candidate passes, into an error propagating path group related to the fault candidate, and stores fault candidates in the group in said fault candidate classification storage unit as a fault candidate group; and inter-pattern overlapping means that calculates combinations of the fault candidate groups that can reproduce the test result in all test patterns by referencing the logic circuit configuration information stored in said logic circuit information storage unit, the fault candidates stored in said single-fault diagnosis result storage unit, and the fault candidate groups stored in said fault candidate classification storage unit, stores the calculated combinations in a combination storage unit and, if there are common fault candidates in the calculated fault candidate groups, extracts only the common fault candidates and re-registers the common fault candidates in said fault candidate classification storage unit as a new fault candidate group.
6. The fault location estimation system according to claim 5 , further comprising: multiple-fault simulation checking means that references said logic circuit information storage unit, said single-fault diagnosis result storage unit, said fault candidate classification storage unit, and said combination storage unit to reference the logic circuit configuration information, the signal line expected values, the fault candidates, the fault types of the fault candidates, the fault candidate group information, and the combination information on the fault candidate group information, selects fault candidates from the combinations of the fault candidate groups, one from each fault candidate group, performs multiple-fault simulation assuming a fault based on the fault types of the selected fault candidates, compares the simulation result with the test result, and outputs a combination of the fault candidate groups which matches relatively well with the test result and has a relatively high fault possibility, as well as the fault types of the fault candidates included in the combination of the fault candidate groups.
7. The fault location estimation system according to claim 1 , comprising: single-fault-assumed diagnostic means that assumes a single fault by referencing logic circuit configuration information and signal line expected values stored in a logic circuit information storage unit and that stores fault candidates in the logic circuit, fault types of the fault candidates, and detected error-observation nodes, at which an error arrives from the fault candidates, into a single-fault diagnosis result storage unit; error propagating path extraction means that extracts error propagating paths to an error-observation node through each fault candidate using the logic circuit configuration information and signal line expected values stored in said logic circuit information storage unit and the fault candidates and error-observation nodes stored in said single-fault diagnosis result storage unit and stores the extracted error propagating paths in a fault candidate classification storage unit as error propagating path information; base fault candidate extraction means that uses the logic circuit configuration information stored in said logic circuit information storage unit, the fault candidates and scores of the fault candidates stored in said single-fault diagnosis result storage unit, and the error propagating path information stored in said fault candidate classification storage unit to extract an error propagating path, which has the highest fault possibility, from un-extracted error propagating paths in all test patterns and stores base information in said fault candidate classification storage unit as a base candidate group; and second error propagating path classification means that classifies the paths, through which an error propagates from the base candidate group, into an error propagating path group by referencing the fault candidates and error propagating path information and by referring to the base information, stores fault candidates, included in a base path in the group, in the combination storage unit as a fault candidate group and, if there is an unselected base candidate group, repeats the grouping operation.
8. The fault location estimation system according to claim 7 , further comprising: multiple-fault simulation checking means that references said logic circuit information storage unit, said single-fault diagnosis result storage unit, said fault candidate classification storage unit, and said combination storage unit to reference the logic circuit configuration information, the signal line expected values, the fault candidates, the fault types of the fault candidates, the fault candidate group information, and combination information on the fault candidate group information, selects fault candidates from combinations of the fault candidate groups, one from each fault candidate group, performs multiple-fault simulation assuming a fault based on the fault types of the selected fault candidates, compares the simulation result with the test result, and outputs a combination of the fault candidate groups which matches relatively well with the test result and has a relatively high fault possibility, as well as the fault types of the fault candidates included in the combination of the fault candidate groups.
9. The fault location estimation system according to claim 1 , wherein said output means outputs, relating multiple fault assumed estimation result, a list of candidate name, fault type and score in each of fault candidate groups.
10. A data process device implemented method of estimating fault location in a logic circuit, said method comprising: classifying locations with a high fault possibility into groups based on error-observation node information acquired from a test result of the logic circuit and that performs fault simulation for confirming and estimating a plurality of fault locations; outputting single-fault estimation results and multiple-fault estimation results, that is, a number of fault candidate groups corresponding to a number of multiple actual faults, fault candidate groups corresponding to each of actual faults, fault candidates included in a fault candidate group, and a fault type of each fault candidate; a single-fault-assumed diagnostic step that assumes a single fault and stores fault candidates in the logic circuit, fault types of the fault candidates, and error-observation nodes at which an error arrives from the fault candidates by referencing logic circuit configuration information and signal line expected values; an error-observation node basis classification step that classifies the fault candidates into groups according to the error-observation nodes using the logic circuit configuration information, the fault candidates, and the error-observation node information and stores the groups in a fault candidate classification storage unit as fault candidate groups; an inclusion fault candidate group selection step that acquires a relation between each fault candidate group and a fault output by referencing the logic circuit configuration information and the fault candidate group information, calculates an inclusion relation among the fault candidate groups, and extracts common candidates; and an inter-pattern overlapping step that calculates combinations of the fault candidate groups that can reproduce the test result in all test patterns by referencing the fault candidates and the fault candidate groups, and, if there are common fault candidates in the calculated fault candidate groups, extracts only the common fault candidates and re-registers the common fault candidates as a new fault candidate group.
11. The method according to claim 10 , further comprising: a multiple-fault simulation checking step that references the logic circuit configuration information, the signal line expected values, the fault candidates, the fault types of the fault candidates, the fault candidate group information, and the combination information on the fault candidate group information, selects fault candidates from the combinations of the fault candidate groups, one from each fault candidate group, performs multiple-fault simulation assuming a fault based on the fault types of the selected fault candidates, compares the simulation result with the test result, and outputs a combination of the fault candidate groups, which matches relatively well with the test result and has a relatively high fault possibility, as well as the fault types of the fault candidates included in the combination of the fault candidate groups.
12. The method according to claim 10 , comprising: a fan-in cone classification step that performs a fan-in trace from error-observation nodes by referencing logical circuit configuration information, classifies traced in-circuit nodes into groups according to error-observation nodes, and stores the grouped result; an in-node-group fault candidate extraction step that extracts signal lines for each node group by referencing the logic circuit configuration information, signal line expected values, and the node groups related to the error-observation nodes, performs single-fault simulation assuming a fault by referencing signal line logic states, and stores signal lines, through which a fault propagates to the error-observation nodes related to the node groups, as fault candidates; an inclusion fault candidate group selection step that acquires a relation between each fault candidate group and a fault output by referencing the logic circuit configuration information and fault candidate group information, calculates an inclusion relation among the fault candidate groups, and extracts common candidates; and an inter-pattern overlapping step that calculates combinations of the fault candidate groups that can reproduce the test result in all test patterns by referencing the fault candidates and the fault candidate groups and, if there are common fault candidates in the calculated fault candidate groups, extracts only the common fault candidates and re-registers the common fault candidates as a new fault candidate group.
13. The method according to claim 10 , comprising: a single-fault-assumed diagnostic step that assumes a single fault by referencing logic circuit configuration information and signal line expected values and that stores fault candidates in the logic circuit, fault types of the fault candidates, and detected error-observation nodes at which an error arrives from the fault candidates; an error propagating path extraction step that extracts error propagating paths to an error-observation node through each fault candidate using the logic circuit configuration information, signal line expected values, fault candidates, and error-observation nodes and stores the extracted error propagating paths as error propagating path information; an error propagating path classification step that selects a candidate with a relatively high fault possibility considering scores of the fault candidates by referencing the fault candidates and the error propagating path information, classifies error propagating paths, related to an error propagating path through which the selected fault candidate passes, into an error propagating path group related to the fault candidate, and stores fault candidates in the group as a fault candidate group; and an inter-pattern overlapping step that calculates combinations of the fault candidate groups that can reproduce the test result in all test patterns by referencing the fault candidates and the fault candidate groups and, if there are common fault candidates in the calculated fault candidate groups, extracts only the common fault candidates, and re-registers the common fault candidates as a new fault candidate group.
14. The method according to claim 10 , comprising: a single-fault-assumed diagnostic step that assumes a single fault by referencing logic circuit configuration information and signal line expected values and that stores fault candidates in the logic circuit, fault types of the fault candidates, and detected error-observation nodes, at which an error arrives from the fault candidates; an error propagating path extraction step that extracts error propagating paths to an error-observation node through each fault candidate using the logic circuit configuration information, the signal line expected values, the fault candidates, and the error-observation nodes and stores the extracted error propagating paths as error propagating path information; a base fault candidate extraction step that uses the logic circuit configuration information, the fault candidates, scores of the fault candidates, and the error propagating path information to extract an error propagating path, which has the highest fault possibility, from un-extracted error propagating paths in all test patterns and stores base information in said fault candidate classification storage unit as a base candidate group; and a second error propagating path classification step that classifies the paths, through which an error propagates from the base candidate group, into an error propagating path group by referencing the fault candidates and error propagating path information and by referring to the base information, stores fault candidates, included in a base path in the group, as a fault candidate group and, if there is an unselected base candidate group, repeats the grouping operation.
15. The method according to claim 10 , wherein relating multiple fault assumed estimation result, a list of candidate name, fault type and score is output in each of fault candidate groups.
16. A program embodied on a non-transitory computer readable medium and causing a computer to estimate fault locations in a logic circuit, said program causing said computer to execute the processing of: classifying locations with a high fault possibility into groups based on error-observation node information acquired from a test result of the logic circuit and performing fault simulation for confirming and estimating a plurality of fault locations; outputting single-fault estimation results and multiple-fault estimation results, that is, a number of fault candidate groups corresponding to a number of multiple actual faults, fault candidate groups corresponding to each of actual faults, fault candidates included in a fault candidate group, and a fault type of each fault candidate; a single-fault-assumed diagnostic process that narrows fault locations in the logic circuit assuming a single fault by referencing logic circuit configuration information and signal line expected values and that stores fault candidates in the logic circuit, types of the faults, and detected error-observation nodes at which an error arrives from the fault candidates which are a result of narrowing the fault locations; an error-observation node basis classification process that classifies the fault candidates into groups according to the error-observation nodes using the logic circuit configuration information, the fault candidates acquired from a medium in which the fault candidates are stored by an existing fault location estimation method, and the error-observation node information and stores the groups in a fault candidate classification storage unit as fault candidate groups; an inclusion fault candidate group selection process that acquires a relation between each fault candidate group and a fault output by referencing the logic circuit configuration information and the fault candidate group information, calculates an inclusion relation among the fault candidate groups, and extracts common candidates; and an inter-pattern overlapping process that calculates combinations of the fault candidate groups that can reproduce the test result in all test patterns by referencing the fault candidates and the fault candidate groups and, if there are common fault candidates in the calculated fault candidate groups, extracts only the common fault candidates and re-registers the common fault candidates as a new fault candidate group.
17. The program according to claim 16 , further causing said computer to execute: a multiple-fault simulation checking process that references the logic circuit configuration information, the signal line expected values, the fault candidates, the fault types of the fault candidates, the fault candidate group information, and the combination information on the fault candidate group information, selects fault candidates from the combinations of the fault candidate groups, one from each fault candidate group, performs multiple-fault simulation assuming a fault based on the fault types of the selected fault candidates, compares the simulation result with the test result, and outputs a combination of the fault candidate groups, which matches relatively well with the test result and has a relatively high fault possibility, as well as the fault types of the fault candidates included in the combination of the fault candidate groups.
18. The program according to claim 16 , causing said computer to execute: a fan-in cone classification process that performs a fan-in trace from error-observation nodes by referencing logical circuit configuration information, classifies traced in-circuit nodes into groups according to error-observation nodes, and stores the grouped result; an in-node-group fault candidate extraction process that extracts signal lines for each node group by referencing the logic circuit configuration information, signal line expected values, and the node groups related to the error-observation nodes, performs single-fault simulation assuming a fault by referencing signal line logic states, and stores signal lines, through which a fault propagates to the error-observation nodes related to the node groups, as fault candidates; an inclusion fault candidate group selection process that acquires a relation between each fault candidate group and a fault output by referencing the logic circuit configuration information and fault candidate group information, calculates an inclusion relation among the fault candidate groups, and extracts common candidates; and an inter-pattern overlapping process that calculates combinations of the fault candidate groups that can reproduce the test result in all test patterns by referencing the fault candidates and the fault candidate groups and, if there are common fault candidates in the calculated fault candidate groups, extracts only the common fault candidates and re-registers the common fault candidates as a new fault candidate group.
19. The program according to claim 16 , causing said computer to execute: a single-fault-assumed diagnostic process that assumes a single fault by referencing logic circuit configuration information and signal line expected values and that stores fault candidates in the logic circuit, fault types of the fault candidates, and detected error-observation nodes at which an error arrives from the fault candidates; an error propagating path extraction process that extracts error propagating paths to an error-observation node through each fault candidate using the logic circuit configuration information, signal line expected values, fault candidates, and error-observation nodes and stores the extracted error propagating paths as error propagating path information; an error propagating path classification process that selects a candidate with a relatively high fault possibility considering scores of the fault candidates by referencing the fault candidates and the error propagating path information, classifies error propagating paths, related to an error propagating path through which the selected fault candidate passes, into an error propagating path group related to the fault candidate, and stores fault candidates in the group as a fault candidate group; and an inter-pattern overlapping process that calculates combinations of the fault candidate groups that can reproduce the test result in all test patterns by referencing the fault candidates and the fault candidate groups and, if there are common fault candidates in the calculated fault candidate groups, extracts only the common fault candidates, and re-registers the common fault candidates as a new fault candidate group.
20. The program according to claim 16 , causing said computer to execute: a single-fault-assumed diagnostic process that uses a program, which executes an existing single-fault location estimation method, by referencing logic circuit configuration information and signal line expected values and that stores fault candidates in the logic circuit, fault types of the fault candidates, and detected error-observation nodes, at which an error arrives from the fault candidates; an error propagating path extraction process that extracts error propagating paths to an error-observation node through each fault candidate using the logic circuit configuration information, the signal line expected values, the fault candidates, and the error-observation nodes and stores the extracted error propagating paths as error propagating path information; a base fault candidate extraction process that uses the logic circuit configuration information, the fault candidates, scores of the fault candidates, and the error propagating path information to extract an error propagating path, which has the highest fault possibility, from un-extracted error propagating paths in all test patterns and stores base information in a fault candidate classification storage unit as a base candidate group; and a second error propagating path classification process that classifies the paths, through which an error propagates from the base candidate group, into an error propagating path group by referencing the fault candidates and error propagating path information and by referring to the base information, stores fault candidates, included in a base path in the group, as a fault candidate group and, if there is an unselected base candidate group, repeats the grouping operation.
21. The program according to claim 16 , causing said computer to output, relating multiple fault assumed estimation result, a list of candidate name, fault type and score in each of fault candidate groups.
Unknown
November 30, 2010
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