Tcp Receiver Acceleration

1. A method for handling network protocol packets, the method comprising: performing by one or more processors and/or circuits integrated within a single chip: classifying via a first hardware module, a header portion of a received packet based on connection context information within said received packet, wherein said connection context information is acquired by said single chip from a memory external to said single chip, and is stored in a memory on said single chip; updating via a second hardware module, said connection context information for said received packet based on said classifying, said second hardware module comprising at least one circuit that processes said connection context information responsive to said classifying; and communicating via a third hardware module, at least a payload portion of said received packet to a destination, based on said updated connection context information, wherein said first hardware module said second hardware module and said third hardware module operate asynchronously.

2. The method according to claim 1 , comprising parsing by said first hardware module, said header portion of said received packet.

3. The method according to claim 1 , comprising validating by said first hardware module, said header portion of said received packet.

4. The method according to claim 1 , comprising evaluating by said second hardware module, said connection context information of said received packet.

5. The method according to claim 1 , comprising evaluating by said second hardware module, said updated connection context information.

6. The method according to claim 1 , comprising executing said classifying by said first processing module during a first processing stage.

7. The method according to claim 1 , comprising executing said classifying by said first processing module at a first processing stage during a first period of time.

8. The method according to claim 7 , comprising executing said updating by said second processing module at a second processing stage during a second period of time, said second period of time independent of said first period of time.

9. The method according to claim 1 , wherein said connection context information is for an established connection.

10. The method according to claim 9 , wherein said memory comprises fast access memory.

11. The method according to claim 1 , comprising determining via said first hardware module, based on said connection context information, whether said received packet is marked for hardware acceleration processing.

12. The method according to claim 11 , comprising if said received packet is marked for said hardware acceleration processing, accelerating via said first hardware module, processing of said received packet.

13. The method according to claim 11 , comprising if said received packet is not marked for said hardware acceleration processing, passing said received packet to a host processor for non-accelerated processing in software.

14. The method according to claim 1 , comprising identifying via said second hardware module, whether a connection is to be removed based on at least one of: said connection context information and/or said updated connection context information.

15. The method according to claim 14 , comprising if said connection is to be removed, instructing via said second hardware module, a synchronization module integrated within said chip to remove said connection.

16. The method according to claim 1 , wherein said first hardware module comprises an analysis engine.

17. The method according to claim 1 , wherein said first hardware module comprises at least one reduced instruction set computer (RISC) processor.

18. The method according to claim 1 , wherein said second hardware module comprises a context processing engine.

19. The method according to claim 1 , wherein said second hardware module comprises at least one reduced instruction set computer (RISC) processor.

20. The method according to claim 1 , wherein said third hardware module comprises a data dispatch engine.

21. The method according to claim 1 , wherein said third hardware module comprises at least one reduced instruction set computer (RISC) processor.

22. The method according to claim 1 , wherein said first hardware module is integrated within a chip.

23. The method according to claim 22 , wherein said second hardware module is integrated within said chip.

24. The method according to claim 23 , wherein said third hardware module is integrated within said chip.

25. A system for handling network protocol packets, the system comprising: a first hardware module that classifies a header portion of a received packet based on connection context information within said received packet; a second hardware module that updates said connection context information for said received packet based on said classifying, said second hardware module comprising at least one circuit that processes said connection context information responsive to said classifying; and a third hardware module that communicates at least a payload portion of said received packet to a destination based on said updated connection context information, wherein said first hardware module, said second hardware module and said third hardware module operate asynchronously and integrated in a single chip, and wherein said connection context information is acquired by said single chip from a memory external to said single chip and stored in a memory on said single chip.

26. The system according to claim 25 , wherein said first hardware module parses said header portion of said received packet.

27. The system according to claim 25 , wherein said first hardware module validates said header portion of said received packet.

28. The system according to claim 25 , wherein said second hardware module evaluates said connection context information of said received packet.

29. The system according to claim 25 , wherein said second hardware module evaluates said updated connection context information.

30. The system according to claim 25 , wherein said first processing module executes said classifying during a first processing stage.

31. The system according to claim 25 , wherein said first processing module executes said classifying at said first processing at a first processing stage during a first period of time.

32. The system according to claim 31 , wherein said second processing module enables execution of said updating at a second processing stage during a second period of time, and wherein said second period of time is independent of said first period of time.

33. The system according to claim 25 , wherein said connection context information is for an established connection.

34. The system according to claim 33 , wherein said memory comprises a fast access memory.

35. The system according to claim 25 , wherein said first hardware module determines based on said connection context information, whether said received packet is marked for hardware acceleration processing.

36. The system according to claim 35 , wherein said first hardware module accelerates processing of said received packet, if said received packet is marked for said hardware acceleration processing.

37. The system according to claim 35 , wherein said first hardware module passes said received packet to a host processor for non-accelerated processing in software, if said received packet is not marked for said hardware acceleration processing.

38. The system according to claim 25 , wherein said second hardware module identifies whether a connection is to be removed based on at least one of: said connection context information and/or said updated connection context information.

39. The system according to claim 38 , wherein said second hardware module instructs a synchronization module integrated within said chip to remove said connection, if said connection is to be removed.

40. The system according to claim 25 , wherein said first hardware module comprises an analysis engine.

41. The system according to claim 25 , wherein said first hardware module comprises at least one reduced instruction set computer (RISC) processor.

42. The system according to claim 25 , wherein said second hardware module comprises a context processing engine.

43. The system according to claim 25 , wherein said second hardware module comprises at least one reduced instruction set computer (RISC) processor.

44. The system according to claim 25 , wherein said third hardware module comprises a data dispatch engine.

45. The system according to claim 25 , wherein said third hardware module comprises at least one reduced instruction set computer (RISC) processor.

46. The system according to claim 25 , wherein said first hardware module is integrated in a chip.

47. The system according to claim 46 , wherein said second hardware module is integrated in said chip.

48. The system according to claim 47 , wherein said third hardware module is integrated in said chip.

49. A system for handling network protocol packets, the system comprising: a first processor that classifies a header portion of a received packet based on connection context information within said received packet; a second processor that updates said connection context information for said received packet based on said classifying, said second processor comprising at least one circuit that processes said connection context information responsive to said classifying; and a third processor that communicates at least a payload portion of said received packet to a destination based on said updated connection context information, wherein said first processor, said second processor and said third processor operate asynchronously and are integrated within a single chip, and wherein said connection context information is acquired by said single chip from a memory external to said single chip and stored in a memory on said single chip.

50. The system according to claim 49 , wherein said first processor parses said header portion of said received packet.

51. The system according to claim 49 , wherein said first processor validates said header portion of said received packet.

52. The system according to claim 49 , wherein said second processor evaluates said connection context information of said received packet.

53. The system according to claim 49 , wherein said second processor evaluates said updated connection context information.

54. The system according to claim 49 , wherein said first processor executes said classifying during a first processing stage.

55. The system according to claim 49 , wherein said first processor executes said classifying at said first processing stage during a first period of time.

56. The system according to claim 55 , wherein said second processor enables execution of said updating at a second processing stage during a second period of time, and wherein said second period of time is independent of said first period of time.

57. The system according to claim 49 , wherein said connection context information is for an established connection.

58. The system according to claim 57 , wherein said memory comprises fast access memory.

59. The system according to claim 49 , wherein said first processor determines based on said connection context information, whether said received packet is marked for hardware acceleration processing.

60. The system according to claim 59 , wherein said first processor accelerates processing of said received packet, if said received packet is marked for said hardware acceleration processing.

61. The system according to claim 59 , wherein said first processor passes said received packet to a host processor for non-accelerated processing in software, if said received packet is not marked for said hardware acceleration processing.

62. The system according to claim 49 , wherein said second processor identifies whether a connection is to be removed based on at least one of: said connection context information and/or said updated connection context information.

63. The system according to claim 62 , wherein said second processor instructs a synchronization processor integrated within said chip to remove said connection, if said connection is to be removed.

64. The system according to claim 49 , wherein said first processor comprises an analysis engine.

65. The system according to claim 49 , wherein said first processor comprises at least one reduced instruction set computer (RISC) processor.

66. The system according to claim 49 , wherein said second processor comprises a context processing engine.

67. The system according to claim 49 , wherein said second processor comprises at least one reduced instruction set computer (RISC) processor.

68. The system according to claim 49 , wherein said third processor comprises a data dispatch engine.

69. The system according to claim 49 , wherein said third processor comprises at least one reduced instruction set computer (RISC) processor.

70. The system according to claim 49 , wherein said first processor is integrated in a chip.

71. The system according to claim 70 , wherein said second processor is integrated in said chip.

72. The system according to claim 71 , wherein said third processor is integrated in said chip.