Buffer Device, Buffer Arrangement Method, and Information Processing Apparatus

1. A buffer device that transfers data and is shared by a plurality of CPU cores arranged in a symmetrically inverted manner about a predetermined reference line, each of the CPU cores breaking up a data block into a plurality of data lines and outputting the data lines via a plurality of ports, the buffer device comprising: a plurality of line buffers that correspond to the data lines and are connected to the ports in the CPU cores, wherein when the plurality of CPU cores is two CPU cores each of which includes an odd-number port for outputting an odd-number line of the data lines and an even-number port for outputting an even-number line of the data lines as the ports, and the two CPU cores are arranged symmetrically about the reference line, odd-number line buffers connected to the odd-number ports out of the line buffers are arranged symmetrically about the reference line and even-number line buffers connected to the even-number ports out of the line buffers are arranged symmetrically about the reference line, and when the even-number port of each of the two CPU cores is arranged on the reference line side, the odd-number line buffers are arranged on the reference line side, and when the odd-number port of each of the two CPU cores is arranged on the reference line side, the even-number line buffers are arranged on the reference line side.

2. The buffer device according to claim 1 , further comprising a wiring switching unit that, when the line buffers are divided into a first group and a second group that include odd-number line buffers and even-number line buffers same in number respectively, switches a wiring that connects each of the first group and the second group to the odd-number port and the even-number port of each of the two CPU cores to one of the first group and the second group for data transfer.

3. The buffer device according to claim 2 , wherein the wiring switching unit switches the wiring based on a write destination address contained in the data output from the CPU cores.

4. A buffer arrangement method for a buffer device that transfers data, is shared by a plurality of CPU cores arranged in a symmetrically inverted manner about a predetermined reference line, each of the CPU cores breaking up a data block into a plurality of data lines and outputting the data lines via a plurality of ports, and includes a plurality of line buffers that correspond to the data lines and are connected to the ports in the CPU cores, wherein when the plurality of CPU cores is two CPU cores each of which includes an odd-number port for outputting an odd-number line of the data lines and an even-number port for outputting an even-number line of the data lines as the ports, and the two CPU cores are arranged symmetrically about the reference line, the buffer arrangement method comprising: arranging odd-number line buffers connected to the odd-number ports out of the line buffers symmetrically about the reference line; arranging even-number line buffers connected to the even-number ports out of the line buffers symmetrically about the reference line; arranging the odd-number line buffers on the reference line side when the even-number port of each of the two CPU cores is arranged on the reference line side; and arranging even-number line buffers on the reference line side when the odd-number port of each of the two CPU cores is arranged on the reference line side.

5. The buffer arrangement method according to claim 4 , further comprising switching, when the line buffers are divided into a first group and a second group that include odd-number line buffers and the even-number line buffers same in number respectively, a wiring that connect each of the first group and the second group to the odd-number port and the even-number port of each of the two CPU cores to one of the first group and the second group for data transfer.

6. The buffer arrangement method according to claim 5 , wherein the switching includes switching the wiring based on a write destination address contained in the data output from the CPU cores.

7. An information processing apparatus comprising: a buffer device that transfers data, is shared by a plurality of CPU cores arranged in a symmetrically inverted manner about a predetermined reference line, each of the CPU cores breaking up a data block into a plurality of data lines and outputting the data lines via a plurality of ports, and includes a plurality of line buffers that correspond to the data lines and are connected to the ports in the CPU cores, wherein when the plurality of CPU cores is two CPU cores each of which includes an odd-number port for outputting an odd-number line of the data lines and an even-number port for outputting an even-number line of the data lines as the ports, and the two CPU cores are arranged symmetrically about the reference line, odd-number line buffers connected to the odd-number ports out of the line buffers are arranged symmetrically about the reference line and even-number line buffers connected to the even-number ports out of the line buffers are arranged symmetrically about the reference line, and when the even-number port of each of the two CPU cores is arranged on the reference line side, the odd-number line buffers are arranged on the reference line side, and when the odd-number port of each of the two CPU cores is arranged on the reference line side, the even-number line buffers are arranged on the reference line side.