Multiple Bit Upset Insensitive Error Detection and Correction Circuit for Field Programmable Gate Array Based on Static Random Access Memory Blocks

1. A computer-readable storage medium in which is stored a program for correcting bit errors, said program comprising codes for permitting the computer to perform: a receiving step for receiving original data, the original data having a plurality of data bits; a partitioning step for partitioning a memory buffer into a first portion and a second portion; a first storing step for storing the original data in the first portion of the memory buffer; a modifying step for modifying the original data into modified data; a second storing step for storing the modified data in the second portion of the memory buffer; a comparing step for comparing the original data stored in the first portion of the memory buffer with the modified data stored in the second portion of the memory buffer; a combining step for combining the original data and the modified data to create a final data stream; and, an outputting step for outputting the final data stream.

2. The computer-readable storage medium according to claim 1 , wherein the memory buffer is a SRAM buffer.

3. The computer-readable storage medium according to claim 1 , wherein the modifying step includes inverting original data.

4. The computer-readable storage medium according to claim 1 , wherein the modifying step includes rearranging original data.

5. The computer-readable storage medium according to claim 1 , wherein the comparing step is performed on a reconfigurable computing device.

6. The computer-readable storage medium according to claim 5 , wherein the reconfigurable computing device comprises at least one field programmable gate arrays.

7. A method for detecting and correcting bit errors, comprising the steps of: receiving original data, the original data having a plurality of data bits; partitioning a memory buffer into a first portion and a second portion; storing the original data in the first portion of the memory buffer; modifying the original data into modified data; storing the modified data in the second portion of the memory buffer; comparing the original data stored in the first portion of the memory buffer with the modified data stored in the second portion of the memory buffer; combining the original data and the modified data to create a final data stream; and, outputting the final data stream.

8. The method for detecting and correcting bit errors according to claim 7 , wherein the memory buffer is a SRAM buffer.

9. The method according to claim 7 , wherein the modifying step includes inverting original data.

10. The method according to claim 7 , wherein the modifying step includes rearranging original data.

11. A computer-readable storage medium in which is stored a program for correcting bit errors, said program comprising codes for permitting the computer to perform: a receiving step for receiving original data, the original data having a plurality of data bits; a first calculating step for calculating a first even parity bit and a first odd parity bit based on the received original data; a storing step for storing the original data in a memory buffer; a second calculating step for calculating a second even parity bit and a second odd parity bit based on the stored original data; a comparing step for comparing the first even parity bit with the second even parity bit, and comparing the first odd parity bit with the second odd parity bit; and, an outputting step for outputting a final data stream.

12. The computer-readable storage medium according to claim 11 , wherein the memory buffer is a SRAM buffer.

13. The computer-readable storage medium according to claim 11 , wherein the comparing step is performed on a reconfigurable computing device.

14. The computer-readable storage medium according to claim 13 , wherein reconfigurable computing device comprises at least one field programmable gate array.