Dataflow Fifo Communication Buffer Using Highly-Multiported Memories

1. A system for transmitting data, the system comprising: a data source; a first data sink; a second data sink; a First-In-First-Out (FIFO) communication buffer having a data input connected to the data source and a data output connected to the first data sink and to the second data sink; and a FIFO connection circuit that connects to the FIFO communication buffer, wherein: the FIFO connection circuit receives a stall signal from the first data sink or the second data sink to indicate when either the first data sink or the second data sink is busy, the FIFO connection circuit separates the stall signal from the first data sink or the second data sink and provides a responsive stall signal to the data source, and the FIFO connection circuit receives a data valid signal from the FIFO communication buffer indicating the FIFO communication buffer has data to send from the source, the FIFO connection circuit providing a responsive data valid signal to the first data sink and the second data sink, wherein based on control signals from the FIFO connection circuit, the data is sent directly from the FIFO communication buffer to the first data sink or the second data sink bypassing the FIFO connection circuit.

2. The system of claim 1 , wherein a same data element is read out of the FIFO communication buffer during each clock cycle by the first sink and the second sink.

3. The system of claim 1 , further comprising: at least one additional data sink, wherein the FIFO communication buffer has data outputs connected to the at least one additional data sink, and wherein the FIFO connection circuit receives a stall signal from the at least one additional data sink to indicate when the at least one additional data sink is busy, the FIFO connection circuit then providing the responsive stall signal to the data source, and wherein the FIFO connection circuit receives a data valid signal from the FIFO memory indicating the FIFO communication buffer has data to send from the source, the FIFO connection circuit providing the responsive data valid signal to the at least one additional data sink.

4. The system of claim 1 , wherein the system comprises a Field Programmable Gate Array (FPGA).

5. The system of claim 1 , wherein responsive to the FIFO connection circuit receiving a data valid signal from the FIFO communication buffer indicating the FIFO communication buffer has data to send from the source, the FIFO connection circuit is configured to provide a data valid signal to the first data sink and the second data sink concurrently.

6. A system for transmitting data, the system comprising: a first First In First Out (FIFO) communication buffer having a data input and input control terminals, and a data output and output control terminals; a first data sink connected to the data output and the output control terminals of the first FIFO communication buffer; a second FIFO communication buffer having a data input and input control terminals, and a data output and output control terminals; a second data sink connected to the data output and the output control terminals of the second FIFO communication buffer; a data source having a data terminal connected to the data input of the first FIFO communication buffer and the second FIFO communication buffer, and control terminals; and a FIFO connection circuit configured to provide a source stall signal to the control terminals of the data source and receive a first stall signal from the first FIFO communication buffer and a second stall signal from the second FIFO communication buffer, wherein the FIFO connection circuit is configured to assert the source stall signal responsive to assertion of either the first stall signal or the second stall signal, and wherein based on control signals from the FIFO connection circuit, data is passed from the data terminal of the data source to the first FIFO communication buffer and the second FIFO communication buffer bypassing the FIFO connection circuit.

7. The system of claim 6 , further comprising: at least one additional FIFO communication buffer having a data input and input control terminals, and a data output and output control terminals; at least one additional data sink connected to the data output and the output control terminals of the at least one additional FIFO communication buffer, wherein the data source has a data terminal connected to the data input of the at least one additional FIFO communication buffer, and wherein the FIFO connection circuit connects the control terminals of the data source to the input control terminals of the at least one additional FIFO communication buffer so that the data from the data source can be received at the at least one additional FIFO communication buffer.

8. The system of claim 6 , wherein the first data sink and the second data sink are configured to read different portions of data sent from the data source and received within the first and second FIFO communication buffers respectively at a same time.

9. The system of claim 6 , wherein the data source sends data to the first FIFO communication buffer and the second FIFO communication buffer concurrently.

10. The system of claim 6 , wherein the FIFO connection circuit is further configured to receive a valid data signal from the data source and assert a valid FIFO signal to the first FIFO communication buffer and the second FIFO communication buffer, wherein the FIFO connection circuit initiates a data transfer from the data source to the first FIFO communication buffer and the second FIFO communication buffer by asserting the valid FIFO signal to each of the first FIFO communication buffer and the second FIFO communication buffer responsive to assertion of the valid data signal from the data source.