Memory Mapped Register File

1. A register system for a data processing system, the register system comprising: an address encoder that generates an encoded address based on (i) a processor mode identifier and (ii) a register identifier, wherein the processor mode identifier identifies P processor modes, and wherein the register identifier identifies one of 2 T−1 unbanked registers, where T and P are integers greater than two; and memory comprising the 2 T−1 unbanked registers, wherein the encoded address identifies one of the 2 T−1 unbanked registers associated with one of the P processor modes, wherein the encoded address consists of T bits.

2. The register system of claim 1 , further comprising: a latch that latches the encoded address from the address encoder; and a selector that selects the encoded address from one of the latch and the address encoder.

3. The register system of claim 1 , further comprising: a source index input; and a source data output, wherein the register identifier is received from the source index input, and wherein the memory outputs data addressed from one of the 2 T−1 unbanked registers identified by the encoded address to the source data output.

4. The register system of claim 1 , further comprising: a write index input; and a write data input, wherein the register identifier is received from the write index input, and wherein the memory inputs data from the write data input to one of the 2 T−1 unbanked registers identified by the encoded address.

5. The register system of claim 1 , wherein the processor mode includes exception handling modes.

6. The register system of claim 5 , wherein the exception handling modes include at least one of a fast interrupt request (FIQ) mode, interrupt request (IRQ) mode, supervisor (SVC) mode, undefined instruction (UND), and abort exception (ABT) mode.

7. The register system of claim 6 , wherein each of the exception handling modes corresponds to at least one of the 2 T−1 unbanked registers.

8. A data processing system, comprising: a microprocessor comprising: a plurality of pipeline stages including a register system, wherein the register system includes: an address encoder that generates an encoded address based on (i) a processor mode identifier and (ii) a register identifier, wherein the processor mode identifier identifies P processor modes, and wherein the register identifier identifies one of 2 T−1 unbanked registers, where T and P are integers greater than two; and memory comprising the 2 T−1 unbanked registers, wherein the encoded address identifies one of the 2 T−1 unbanked registers associated with one of the P processor modes, wherein the encoded address consists of T bits.

9. The data processing system of claim 8 , further comprising: a latch that latches the encoded address from the address encoder; and a selector that selects the encoded address from one of the latch and the address encoder.

10. The data processing system of claim 8 , further comprising: a source index input; and a source data output, wherein the register identifier is received from the source index input, and wherein the memory outputs data addressed from one of the 2 T−1 unbanked registers identified by the encoded address to the source data output.

11. The data processing system of claim 8 , further comprising: a write index input; and a write data input, wherein the register identifier is received from the write index input, and wherein the memory inputs data from the write data input to one of the 2 T−1 unbanked registers identified by the encoded address.

12. The data processing system of claim 8 , wherein the processor mode includes exception handling modes.

13. The data processing system of claim 12 , wherein the exception handling modes include at least one of a fast interrupt request (FIQ) mode, interrupt request (IRQ) mode, supervisor (SVC) mode, undefined instruction (UND), and abort exception (ABT) mode.

14. The data processing system of claim 13 , wherein each of the exception handling modes corresponds to at least one of the 2 T−1 unbanked registers.