7890558

Apparatus and Method for Precision Binary Numbers and Numerical Operations

PublishedFebruary 15, 2011
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
31 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method, comprising: controlling an output device via an output interface, wherein controlling the output device comprises: storing a first integer portion and a first integer sign bit of a first numerical value in a first storage area of a computer, and storing a first fractional portion and a first fractional portion sign bit of the first numerical value in a second storage area of the computer.

2

2. The method according to claim 1 wherein the first fractional portion is stored in the second storage area according to a standard binary integer format.

3

3. The method according to claim 2 wherein the first fractional portion is stored in the second storage area as a signed 2's complement binary integer.

4

4. The method according to claim 1 wherein the first fractional portion is stored in the second storage area according to a standard binary integer format.

5

5. The method according to claim 4 wherein the first fractional portion is multiplied by a scale value and then stored in the second storage area according to a standard binary integer format.

6

6. The method according to claim 5 wherein the scale value is an integer power of 10.

7

7. The method according to claim 4 wherein the first fractional portion is stored in the second storage area as a signed 2's complement binary integer.

8

8. The method according to claim 1 further comprising: determining character codes for the first numerical value by separately determining character codes for the first integer portion and the first fractional portion; and concatenating separately determined character codes to provide character codes for the first numerical value.

9

9. An information processing apparatus comprising one or more logic modules configured to perform the method as recited in claim 1 .

10

10. A tangible computer readable medium storing logical instructions that, responsive to execution by into an appropriately configured digital apparatus, cause the apparatus to operate in accordance with the method of claim 1 .

11

11. The method of claim 1 , further comprising: storing a second integer portion and a second integer sign bit of a second numerical value in a third storage area of the computer; and storing a second fractional portion and a second fractional portion sign bit of the second numerical value in a fourth storage area of the computer.

12

12. The method of claim 11 , further comprising performing an addition operation on the first numerical value and the second numerical value, wherein the addition operation comprises: storing a third fractional portion, where the third fractional portion is a sum of the first fractional portion and the second fractional portion; setting a carry value equal to zero; comparing the third fractional portion to a maximum fractional portion value; responsive to determining third fractional portion exceeds the maximum fractional portion value: setting the carry value equal to one, and subtracting a value of the maximum fractional portion value plus one from the third fractional portion; setting a third integer portion equal to a sum of the first integer portion, the second integer portion, and the carry value; determining that both the first real value and the second real value are negative; and in response to determining that both the first real value and the second real value are negative, negating both a third fractional portion sign bit and a third integer portion sign bit.

13

13. The method of claim 11 , further comprising performing a subtraction operation on the first numerical value and the second numerical value, wherein the subtraction operation comprises: in response to a determination that the first integer portion is greater than the second integer portion and that the second fractional portion is greater than the first fractional portion: subtracting one from the first integer portion, and adding a maximum fractional portion value plus one to the first fractional portion; in response to a determination that the second integer portion is greater than the first integer portion and that the first fractional portion is greater than the second fractional portion: subtracting one from the second integer portion, and adding the maximum fractional portion value plus one to the second fractional portion; storing a third integer portion, where the third integer portion is a result of subtracting the first integer portion from the second integer portion; and storing a third fractional portion, where the third fractional portion is a result of subtracting the first fractional portion from the second fractional portion.

14

14. The method of claim 11 , further comprising performing a multiplication operation on the first numerical value and the second numerical value based on the first and second integer portions and the first and second fractional portions.

15

15. The method of claim 11 , further comprising performing a division operation on the first numerical value and the second numerical value based on the first integer and second portions and the first and second fractional portions.

16

16. A device comprising: means for interfacing output; means for controlling an output device via the means for interfacing output, wherein the means for controlling the output device comprises: means for storing integer portions of numerical values, configured to store a first integer portion and a first integer sign bit of a first numerical value; and means for storing fractional portions of the numerical values, configured to store a first fractional portion and a first fractional portion sign bit of the first numerical value.

17

17. The device of claim 16 further wherein: the first integer portion of the first numerical value is stored using a standard binary integer format.

18

18. The device of claim 16 further wherein: the first fractional portion of the first numerical value is multiplied by a scale value and then stored in the means for storing fractional portions using a standard binary integer format.

19

19. The device of claim 16 further comprising: means for determining character codes for a numerical value stored as an integer portion and an fractional portion configured to separately determine character codes for the integer portion and the fractional portion.

20

20. The device of claim 16 , wherein the means for storing integer portions are further configured to store a second integer portion and a second integer sign bit of a second numerical value, and wherein means for storing fractional portions are further configured to store a second fractional portion and a second fractional portion sign bit of the second numerical value.

21

21. The device of claim 20 , further comprising means for adding the first numerical value and the second numerical value, wherein the means for adding comprise: means for storing a third fractional portion, where the third fractional portion is a sum of the first fractional portion and the second fractional portion; means for setting a carry value equal to zero; means for comparing the third fractional portion to a maximum fractional portion value; means for, responsive to determining third fractional portion exceeds the maximum fractional portion value: setting the carry value equal to one, and subtracting a value of the maximum fractional portion value plus one from the third fractional portion; means for setting a third integer portion equal to a sum of the first integer portion, the second integer portion, and the carry value; means for determining that both the first real value and the second real value are negative; and means for negating both a third fractional portion sign bit and a third integer portion sign bit, in response to determining that both the first real value and the second real value are negative.

22

22. The device of claim 20 , further comprising means for subtracting the first numerical value and the second numerical value, wherein the means for subtracting comprise: means for, in response to a determination that the first integer portion is greater than the second integer portion and that the second fractional portion is greater than the first fractional portion: subtracting one from the first integer portion, and adding a maximum fractional portion value plus one to the first fractional portion; means for, in response to a determination that the second integer portion is greater than the first integer portion and that the first fractional portion is greater than the second fractional portion: subtracting one from the second integer portion, and adding the maximum fractional portion value plus one to the second fractional portion; means for storing a third integer portion, where the third integer portion is a result of subtracting the first integer portion from the second integer portion; and means for storing a third fractional portion, where the third fractional portion is a result of subtracting the first fractional portion from the second fractional portion.

23

23. The device of claim 20 , further comprising means for multiplying the first numerical value and the second numerical value based on the first and second integer portions and the first and second fractional portions.

24

24. The device of claim 20 , further comprising performing a division operation on the first numerical value and the second numerical value based on the first integer and second portions and the first and second fractional portions.

25

25. An apparatus, comprising: a processor; an output interface; a memory; and instructions, stored in the memory, that responsive to execution by the processor, cause the apparatus to perform operations comprising: controlling an output device via the output interface, wherein controlling the output device comprises: storing a first integer portion and a first integer sign bit of a first numerical value in a first storage area of the memory and storing a first fractional portion and a first fractional portion sign bit of the first numerical value in a second storage area of the memory.

26

26. The apparatus of claim 25 , wherein the first fractional portion is multiplied by a scale value and then stored in the second storage area according to a standard binary integer format, and wherein the scale value is an integer power of 10.

27

27. The apparatus of claim 25 , wherein the operations further comprise: storing a second integer portion and a second integer sign bit of a second numerical value in a third storage area of the computer; and storing a second fractional portion and a second fractional portion sign bit of the second numerical value in a fourth storage area of the computer.

28

28. The apparatus of claim 27 , wherein the operations further comprise performing an addition operation on the first numerical value and the second numerical value, and wherein the addition operation comprises: storing a third fractional portion, where the third fractional portion is a sum of the first fractional portion and the second fractional portion; setting a carry value equal to zero; comparing the third fractional portion to a maximum fractional portion value; responsive to determining third fractional portion exceeds the maximum fractional portion value: setting the carry value equal to one, and subtracting a value of the maximum fractional portion value plus one from the third fractional portion; setting a third integer portion equal to a sum of the first integer portion, the second integer portion, and the carry value; determining that both the first real value and the second real value are negative; and in response to determining that both the first real value and the second real value are negative, negating both a third fractional portion sign bit and a third integer portion sign bit.

29

29. The apparatus of claim 27 , wherein the operations further comprise performing a subtraction operation on the first numerical value and the second numerical value, and wherein the subtraction operation comprises: in response to a determination that the first integer portion is greater than the second integer portion and that the second fractional portion is greater than the first fractional portion: subtracting one from the first integer portion, and adding a maximum fractional portion value plus one to the first fractional portion; in response to a determination that the second integer portion is greater than the first integer portion and that the first fractional portion is greater than the second fractional portion: subtracting one from the second integer portion, and adding the maximum fractional portion value plus one to the second fractional portion; storing a third integer portion, where the third integer portion is a result of subtracting the first integer portion from the second integer portion; and storing a third fractional portion, where the third fractional portion is a result of subtracting the first fractional portion from the second fractional portion.

30

30. The apparatus of claim 27 , wherein the operations further comprise performing a multiplication operation on the first numerical value and the second numerical value based on the first and second integer portions and the first and second fractional portions.

31

31. The apparatus of claim 27 , wherein the operations further comprise performing a division operation on the first numerical value and the second numerical value based on the first integer and second portions and the first and second fractional portions.

Patent Metadata

Filing Date

Unknown

Publication Date

February 15, 2011

Inventors

Daniel Esbensen

Want to explore more patents?

Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.

Citation & reuse

Analysis on this page is generated by Patentable — an AI-powered patent intelligence platform. AI-generated summaries, explanations, and analysis may be reused with attribution and a visible link back to the canonical URL below. Patent abstracts and claims are USPTO public domain.

Cite as: Patentable. “APPARATUS AND METHOD FOR PRECISION BINARY NUMBERS AND NUMERICAL OPERATIONS” (7890558). https://patentable.app/patents/7890558

© 2026 Patentable. All rights reserved.

Patentable is a research and drafting-assistant tool, not a law firm, and does not provide legal advice. Documents we generate are drafts for review by a licensed patent attorney.