Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of providing a clock signal in a digital frequency synthesizer, the method comprising: receiving a plurality of digital frequency signals, each of the digital frequency signals being provided at a distinct frequency; and controlling an array of switches, wherein an input of each switch is coupled to receive a respective one of the digital frequency signals, wherein an output of each of the switches is coupled to a clock output for providing the clock signal, wherein the switches are controlled so that the clock signal has an average frequency between a highest frequency of the digital frequency signals and a lowest frequency of the digital frequency signals, wherein the controlling is performed by a delta sigma modulator.
2. The method of claim 1 , wherein the delta sigma modulator receives a fractional input.
3. The method of claim 1 , wherein the digital synthesizer is utilized in a wireless communication device.
4. The method of claim 1 , wherein wideband modulation is obtained.
5. The method of claim 3 , wherein the delta sigma modulator includes fraction input.
6. The method of claim 5 , wherein the digital frequency synthesizer is entirely integrated on at least one of a CMOS, bi-CMOS, silicon germanium, gallium arsenide device.
7. A method of digital frequency synthesis, the method comprising: providing a first signal at a first frequency, wherein the first signal is received at a first input of a first switch; providing a second signal at a second frequency, wherein the second signal is received at a first input of a second switch; providing a third signal at a third frequency, wherein the third signal is received at a first input of a third switch, wherein outputs of the first, second, and third switches are coupled to a clock node; and controlling the first, second, and third switch so that a clock signal at the clock node has an average frequency, the average frequency being within a range of the first frequency, the second frequency and the third frequency, wherein the controlling is performed by a delta sigma modulator.
8. The method of digital frequency synthesis of claim 7 , wherein wideband modulation is obtained.
9. A method of providing a clock signal in a digital frequency synthesizer, the method comprising: receiving a plurality of digital frequency signals, each of the digital frequency signals being provided at a distinct frequency; controlling an array of switches, wherein an input of each switch is coupled to receive a respective one of the digital frequency signals, wherein an output of each of the switches is coupled to a clock output for providing the clock signal, wherein the switches are controlled so that the clock signal has an average frequency between a highest frequency of the digital frequency signals and a lowest frequency of the digital frequency signals, wherein the controlling is performed by a delta sigma modulator; and providing the clock signal to a clean-up phase locked loop.
10. The method of digital frequency synthesis of claim 9 , wherein the controlling is performed by a delta sigma modulator.
11. A method of digital frequency synthesis, comprising: receiving a plurality of digital frequency signals at a plurality of switches, the digital frequency signals being provided at distinct frequencies; providing control signals to the plurality of switches via a control circuit coupled to the switches, the control signals controlling the switches to select the digital frequency signals to provide an output signal having an average frequency at a first frequency, the average frequency being within a range of the distinct frequencies; and receiving a clock signal at the control circuit, wherein the clock signal is the output signal or is derived from the output signal.
12. The method of digital frequency synthesis of claim 11 , wherein the control circuit includes a dithering circuit.
13. The method of digital frequency synthesis of claim 11 , wherein the control circuit includes a delta-sigma modulator.
14. The method of digital frequency synthesis of claim 11 , wherein wideband modulation is achieved.
15. The method of digital frequency synthesis of claim 11 , wherein the plurality of digital frequency signals are provided by at least one digital delay locked loop.
16. The method of digital frequency synthesis of claim 11 , further comprising: providing the output signal to a phase locked loop.
17. The method of digital frequency synthesis of claim 16 , wherein the phase locked loop includes an integer divider and the phase locked loop provides a cleaner version of the output signal.
18. The method of digital frequency synthesis of claim 11 , wherein the plurality of digital frequency signals are provided by a plurality of digital frequency sources coupled to the switches, the digital frequency sources individually providing the digital frequency signals.
19. The method of digital frequency synthesis of claim 11 , wherein a tone spacing between the digital frequency signals is a fixed amount.
20. The method of digital frequency synthesis of claim 11 , wherein a tone spacing between the digital frequency signals is a non-fixed amount.
Unknown
March 1, 2011
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