Dual Port Memory Device, Memory Device and Method of Operating the Dual Port Memory Device

1. A dual port memory device, comprising: a memory array; a converting unit for converting an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface and dividing an address, which is inputted via the first port and conforms to the first type memory interface, into a row address, a column address and a bank address which conform to the second type memory interface; a first memory interface for performing a read operation or a write operation for the memory array based on the address and the control signal which conform to the second type memory interface; and a second memory interface for performing a read operation or a write operation on the memory array based on an address and a control signal which are inputted via a second port and conform to the second type memory interface.

2. The dual port memory device of claim 1 , wherein the converting unit comprises: a row address extractor for extracting a row address which conform to the second type memory interface from an address which is inputted via the first port and conform to the first type memory interface; a column address extractor for extracting a column address which conform to the second type memory interface from an address which is inputted via the first port and conform to the first type memory interface; and a bank address extractor for extracting a bank address which conform to the second type memory interface from an address which is inputted via the first port and conform to the first type memory interface.

3. The dual port memory device of claim 2 , wherein the converting unit further comprises: a converter for receiving a control signal which is inputted via the first port and conform to the first type memory interface and generating timing information for performing a read operation, a write operation and a refresh operation which conform to the second type memory interface; and a command controller for receiving the timing information and generating a control signal for performing a read operation, a write operation and a refresh operation which conform to the second type memory interface.

4. The dual port memory device of claim 1 , wherein the converting unit converts the address and the control signal which are inputted via the first port and conform to the first type memory interface into the address and the control signal which conform to the second type memory interface through a signal converting path in response to a selecting signal or bypasses the address and the control signal which are inputted via the first port and conform to the second type memory interface through a bypass path.

5. The dual port memory device of claim 4 , wherein the converting unit comprises: a first selector for providing the address and the control signal which are inputted via the first port and conform to the first type memory interface to the signal converting path or providing the address and the control signal which are inputted via the first port and conform to the second type memory interface to the bypass path; a signal converter for converting an address and a control signal which are provided to the signal converting path and conform to the first type memory interface into the address and the control signal which conform to the second type memory interface; and a second selector for selecting an address and a control signal which are bypassed or an address and a control signal which are outputted from the signal converter and conform to the second type memory interface.

6. The dual port memory device of claim 5 , wherein the first type memory interface includes a PSRAM interface, the second type memory interface includes an SDRAM interface, and the signal converter divides an address, which is provided to the signal converting path and conform to the first type memory interface, into a row address, a column address and a bank address which conform to the second type memory interface.

7. A memory device, comprising: a memory array; a converting unit for converting an address and a control signal which are inputted via a first port and conform to a first type memory interface into an address and a control signal which conform to a second type memory interface and dividing the address, which is inputted via the first port and conforms to the first type memory interface, into a row address, a column address and a bank address which conform to the second type memory interface; and a memory interface for performing a read operation or a write operation on the memory array based on the address and the control signal which conform to the second type memory interface.

8. The memory device of claim 7 , wherein the converting unit converts the address and the control signal which are inputted via the first port and conform to the first type memory interface into the address and the control signal which conform to the second type memory interface through a signal converting path in response to a selecting signal or bypasses an address and a control signal which are inputted via the first port and conform to the second type memory interface through a bypass path.

9. The memory device of claim 8 , wherein the converting unit comprises: a first selector for providing the address and the control signal, which are inputted via the first port and conform to the first type memory interface, to the signal converting path or providing an address and a control signal which are inputted via the first port and conform to the second type memory interface to the bypass path; a signal converter for converting an address and a control signal, which are provided to the signal converting path and conform to the first type memory interface, into an address and a control signal which conform to the second type memory interface; and a second selector for selecting an address and a control signal which are bypassed or an address and a control signal which are outputted from the signal converter and conform to the second type memory interface.

10. The memory device of claim 9 , wherein the first type memory interface includes a PSRAM interface, the second type memory interface includes an SDRAM interface, and the signal converter divides an address which is provided to the signal converting path and conform to the first type memory interface into a row address, a column address and a bank address which conform to the second type memory interface.

11. A method of operating a dual port memory device, comprising: converting an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface; dividing an address, which is inputted via the first port and conforms to the first type memory interface, into a row address, a column address and a bank address which conform to the second type memory interface; and performing a read operation or a write operation on the memory array based on the address and the control signal which are inputted via a second port and conform to the second type memory interface.

12. The method of claim 11 , wherein the converting an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface comprises: extracting a row address which conform to the second type memory interface from an address which is inputted via the first port and conform to the first type memory interface; extracting a column address which conform to the second type memory interface from an address which is inputted via the first port and conform to the first type memory interface; and extracting a bank address which conform to the second type memory interface from an address which is inputted via the first port and conform to the first type memory interface.

13. The method of claim 12 , wherein the converting an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface comprises: receiving a control signal which is inputted via the first port and conform to the first type memory interface and generating timing information for performing a read operation, a write operation and a refresh operation which conform to the second type memory interface; and receiving the timing information and generating a control signal which conform to the second type memory interface.

14. The method of claim 11 , wherein the converting an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface comprises: converting the address and the control signal, which are inputted via the first port and conform to the first type memory interface, into an address and a control signal which conform to the second type memory interface through a signal converting path in response to a selecting signal or bypassing an address and a control signal which are inputted via the first port and conform to the second type memory interface through a bypass path; performing a read operation or a write operation on the memory array based on the converted address and control signal while the selecting signal has a non-active state; and performing a read operation or a write operation on the memory array based on the bypassed address and control signal while the selecting signal has an active state.

15. The method of claim 14 , wherein the converting an address and a control signal, which are inputted via the first port and conform to the first type memory interface, into an address and a control signal which conform to the second type memory interface through a signal converting path in response to a selecting signal or bypassing an address and a control signal which are inputted via the first port and conform to the second type memory interface through a bypass path comprises: bypassing an address and a control signal, which are inputted via the first port and conform to the second type memory interface, through the bypass path when the selecting signal gets active; converting an address and a control signal, which are inputted via the first port and conform to the second type memory interface, into an address and a control signal which conform to the second type memory interface through a signal converting path when the selecting signal gets non-active; converting an address and a control signal, which are provided to the signal converting path and conform to the first type memory interface, into an address and a control signal which conform to the second type memory interface; and selecting an address and a control signal which are bypassed or an address and a control signal which are outputted from a signal converter and conform to the second type memory interface.

16. The method of claim 15 , wherein the first type memory interface includes a PSRAM interface, the second type memory interface includes an SDRAM interface, and the converting an address and a control signal, which are provided to the signal converting path and conform to the first type memory interface, into an address and a control signal which conform to the second type memory interface comprises dividing an address, which is provided to the signal converting path and conform to the first type memory interface, into a row address, a column address and a bank address which conform to the second type memory interface.

17. The method of claim 16 , wherein the converting an address and a control signal, which are provided to the signal converting path and conform to the first type memory interface, into an address and a control signal which conform to the second type memory interface comprises: extracting a row address, which conform to the second type memory interface, from an address which is inputted to the signal converting path and conform to the first type memory interface; extracting a column address, which conform to the second type memory interface, from an address which is inputted to the signal converting path and conform to the first type memory interface; and extracting a bank address, which conform to the second type memory interface, from an address which is inputted to the signal converting path and conform to the first type memory interface.

18. The method of claim 17 , wherein the converting an address and a control signal, which are provided to the signal converting path and conform to the first type memory interface, into an address and a control signal which conform to the second type memory interface comprises: receiving a control signal which is inputted to the signal converting path and conform to the first type memory interface and generating timing information for performing a read operation, a write operation and a refresh operation which conform to the second type memory interface; and receiving the timing information and generating a control signal which conform to the second type memory interface.

19. A dual port memory device, comprising: a memory array; a dual interface port including a first selector for providing a first path through which the memory array is accessed according to a first type memory interface based on an address and a control signal which are inputted via a first port or a second path through which the memory array is accessed according to a second type memory interface, in response to a selecting signal, an interface for outputting an address for accessing the memory array and data according to the first type memory interface based on an address and a control signal which are provided through the first path or outputting an address for accessing the memory array and data according to the second type memory interface based on an address and a control signal which are provided through the second path and a second selector for selecting any address of an address for accessing the memory array and data according to the first type memory interface and an address for accessing the memory array and data according to the second type memory interface and data in response to the selecting signal for accessing the memory array according to the first type memory interface or the second type memory interface based on the address and the control signal which are inputted via the first port, in response to the selecting signal; and a first memory interface for accessing the memory array through the second type memory interface based on an address and a control signal which are inputted via a second port.

20. The dual port memory device of claim 19 , wherein the interface comprises: an I/O buffer coupled between the first selector and the second selector and configured to buffer data to access the memory array; a first type memory interface for buffering data to access the memory array in the I/O buffer according to the first type memory interface based on an address and a control signal which are provided through the first path, and decoding and outputting an address which is provided through the first path; and a second type memory interface for buffering data to access the memory array in the I/O buffer according to the second type memory interface based on an address and a control signal which are provided through the second path, and decoding and outputting an address which is provided through the second path.

21. A memory device, comprising: a memory array; and a dual interface port including a first selector for providing a first path through which a memory array is accessed according to a first type memory interface based on an address and a control signal which are inputted via a first port or a second path through which the memory array is accessed according to a second type memory interface, in response to a selecting signal, an interface for outputting an address for accessing a memory array and data according to the first type memory interface based on an address and a control signal which are provided through the first path or outputting an address for accessing the memory array and data according to the second type memory interface based on an address and a control signal which are provided through the second path and a second selector for selecting any address of an address for accessing the memory array and data according to the first type memory interface and an address for accessing the memory array and data according to the second type memory interface and data in response to the selecting signal for accessing the memory array according to the first type memory interface or the second type memory interface based on the address and the control signal which are inputted via the first port, in response to the selecting signal.

22. A method of operating a dual port memory device, comprising: accessing a memory array according to a first type memory interface based on an address and a control signal which are inputted via a first port while a selecting signal has a non-active state; providing a first path through which the memory array is accessed according to the first type memory interface based on an address and a control signal which are inputted via the first port while the selecting signal has the non active state; accessing a memory array according to a second type memory interface based on an address and a control signal which are inputted via the first port while the selecting signal has an active state; and providing a second path through which the memory array is accessed according to the second type memory interface while the selecting signal has the active state.

23. The method of claim 22 , wherein the accessing a memory array according to a first type memory interface based on an address and a control signal which are inputted via a first port while the selecting signal has a non-active state comprises: outputting an address for accessing the memory array and data according to the first type memory interface based on an address and a control signal which are provided through the first path.

24. The method of claim 23 , wherein the accessing a memory array according to a second type memory interface based on an address and a control signal which are inputted via the first port while the selecting signal has an active state comprises: outputting an address for accessing the memory array and data according to the second type memory interface based on an address and a control signal which are provided through the second path.

25. The method of claim 24 , further comprising selecting any of an address for accessing the memory array according to the first type memory interface and an address for accessing the memory array according to the second type memory interface in response to the selecting signal.