Method, Apparatus and Instructions for Parallel Data Conversions

1. An apparatus comprising: a destination storage location corresponding to a first architectural register; an execution unit having circuitry to process a packed format values by converting, responsive to a control signal, a first packed first format value in a first format selected from a first plurality of packed first format values in the first format to a first plurality of second format values, said first packed first format value having a plurality of sub elements each having a first number of bits, each of the first plurality of second format values being a number represented in a second format and having a second number of bits which is greater than the first number of bits, said execution unit to store all of said first plurality of second format values into said first architectural register.

2. The apparatus of claim 1 wherein the second number of bits is a power-of-two multiple of the first number of bits.

3. The apparatus of claim 2 wherein a source specifier is to specify either a second architectural register or a memory location as a source storage location and further wherein a destination specifier is to specify the first architectural register as the destination storage location.

4. The apparatus of claim 3 wherein said first format is an integer format and wherein said second format is a floating point format.

5. The apparatus of claim 4 further comprising: a decoder to receive a single convert instruction, said decoder to generate said control signal in response to the single convert instruction.

6. The apparatus of claim 5 wherein an opcode portion of said single convert instruction specifies which of said first plurality of packed first format values to convert.

7. The apparatus of claim 5 wherein said control signal comprises a micro operation generated by the decoder in response to the single convert instruction.

8. The apparatus of claim 5 further comprising a register renaming circuit, wherein said source storage location and said destination storage location are physical registers that each have a correspondence to an architectural register, said correspondence being tracked by the register renaming circuit.

9. The apparatus of claim 8 wherein said single convert instruction comprises an opcode and an operand specifier, wherein the operand specifier is in a MOD RIM format.

10. The apparatus of claim 8 wherein said first plurality of packed first format values are N bit integer values and wherein said first packed first format value is an N bit integer value, wherein said plurality of sub elements is M sub elements and wherein each of the M sub elements has N/M bits, and further wherein each of the first plurality of second format values is an N-bit floating point result.

11. The apparatus of claim 3 wherein said first architectural register and said second architectural register are part of a first group of architectural registers, the first group of architectural registers having a first size.

12. The apparatus of claim 1 wherein said execution unit chooses one of said first plurality of packed first format values to convert based on an immediate operand value.

13. The apparatus of claim 1 further comprising a second destination storage location, wherein said execution unit is further responsive to a second control signal to convert a second plurality of second format values in the second format having the second number of bits to a second first format value and to store the second first format value in one of a plurality of packed first format value positions in said second destination storage location, wherein said second first format value comprises saturated representations of the second plurality of second format values in the first format.

14. The apparatus of claim 13 wherein first architectural register and said second destination storage location are registers in a group of xmm registers.

15. An apparatus comprising: a decoder to receive a first instruction and to decode said first instruction into a control signal; an execution unit coupled to the decoder the execution unit having circuitry to receive the control signal, the execution unit to responsively process a plurality of floating point values by converting a first plurality of floating point values in a first floating point format having a first number of bits into a first integer value comprising a plurality of sub elements each having a second number of bits less than the first number of bits and to store said first integer value in a first position in a first register, the first register being capable of storing a plurality of integer values in a plurality of individually accessible positions.

16. The apparatus of claim 15 wherein said first instruction comprises an opcode, a first operand specifier, an immediate operand, and a second operand specifier, wherein the first operand specifier specifies a source from which the execution unit is to retrieve the first plurality of floating point values, the second operand specifier specifies the first register from a plurality of registers, and wherein the immediate operand specifies one of a plurality of locations in the first register in which the first integer value is to be stored.

17. The apparatus of claim 16 wherein said decoder is to decode a second instruction and to responsively generate a second signal, and wherein said execution unit, responsive to said second signal, is to convert a second integer value to a second plurality of floating point values in the first floating point format and to store said second plurality of floating point values into a second register.

18. The apparatus of claim 17 wherein said first register and said second register are part of a first group of architectural registers, and further wherein said plurality of sub elements comprise saturated representations of said first plurality of floating point values.

19. The apparatus of claim 18 wherein a second immediate operand is to specify one location of a second plurality of locations within a register from which to retrieve the second integer value.

20. A method comprising: a module fetching a first instruction that specifies a location of a first format value in a first format among a plurality of first format values of a packed data, the first format value having a plurality of sub elements each sub element having a first number of bits; an execution unit processing the first format value by converting the first format value to a first plurality of second format values in a second format with circuitry, each of the first plurality of second format values having the second format and corresponding to one of the plurality of sub elements, the second format having a multiple of the first number of bits; storing the first plurality of second format values into a first register.

21. The method of claim 20 wherein said location is a second register, wherein said first register and said second register are registers in a single group of architectural registers.

22. The method of claim 21 further comprising: fetching a second instruction that specifies a second location of a second plurality of second format values in the second format; converting the second plurality of second format values to a second first format value; storing the second first format value in a third register, wherein the third register is also in the single group of architectural registers.

23. The method of claim 22 further comprising: specifying which of the plurality of first format values to convert by an immediate operand; specifying one a plurality of destination packed data positions for the second first format value with a second immediate operand.

24. The method of claim 22 wherein said first format is an integer format and wherein said second format is a floating point format.

25. The method of claim 24 further comprising: saturating each of the second plurality of second format values to generate a plurality of clamped sub elements of the second first format value.

26. A system comprising: a memory to store a first instruction and an image processing sequence that operates on image data in a second format; a processor coupled to the memory to process a first operand comprising a plurality of packed integer data values according to the first instruction by converting one of the plurality of packed integer data values into a first plurality of values in a second format and to store said first plurality of values in the second format into a register corresponding to an architectural register, said first plurality of values in the second format being manipulated as part of an image by said image processing sequence; a graphics interface coupled to the processor to receive graphical data representative of the image from said processor; a display to display said image.

27. The system of claim 26 wherein said first plurality of values in said second format have a larger total number of bits than said one of said plurality of packed integer data values.

28. The system of claim 26 wherein said memory stores a second instruction to cause the processor to convert a second plurality of values in the second format which are a result of manipulation of said first plurality of values in the second format by said image processing sequence into a second integer data value and to store the second integer data value to a second register corresponding to a second architectural register, and further wherein said second integer data value is written to the graphics interface as a pixel value.

29. The system of claim 28 wherein said first instruction is a first convert instruction, wherein each of the plurality of packed integer data values has a plurality of sub elements each having a first number of bits and wherein each of the first plurality of values corresponds to one of the plurality of sub elements and has a first floating point format having a multiple of the first number of bits.

30. The system of claim 26 wherein said first instruction specifies a first one of the plurality of packed integer data values, and wherein said plurality of packed integer data values comprises N integer data values, wherein the memory stores N convert instructions including the first instruction to convert the N integer data values into a set of N pluralities of floating point values.

31. The system of claim 30 wherein said image processing sequence is to operate on said set of N pluralities of floating point values to generate a second N pluralities of floating point values as a portion of the image, and further wherein said memory stores a second plurality of N convert instructions to convert each of second N pluralities of floating point values back to integer data values in a packed format.

32. A tangible machine readable medium storing an instruction, which if executed by a machine, causes the machine to perform operations of: converting with an arithmetic logic unit an integer value, the integer value being among a plurality of integer values of a packed data and having a first integer format having a plurality of sub elements each having a first number of bits, to a plurality of floating point values, each of the plurality of floating point values having a first floating point format, the first floating point format having a multiple of the first number of bits; storing the plurality of floating point values into a first register, wherein the tangible machine readable medium is one of a memory, a magnetic storage disc, and an optical storage disc.

33. The machine readable medium of claim 32 , wherein said machine readable medium further stores one or more additional instructions, which if executed by the machine, cause the machine to perform: converting a second plurality of floating point values in the first floating point format to a second integer value in the first integer format; storing the second integer value in a third register, wherein the third register is also in a group of architectural registers and is capable of storing a plurality of integer values in the first integer format.