Systems and Methods for Monitoring and Controlling Binary State Devices Using a Memory Device

1. A memory device, comprising: one or more controlling bits, wherein each controlling bit is capable of being set; and one or more controlled register bits coupled to the one or more controlling bits, wherein each controlled register bit is capable of being coupled to an external binary state device, each binary state device being located external to the memory device; wherein the setting of the one or more controlling bits defines which controlled register bits of the one or more controlled register bits are input read register bits and which are output drive register bits; and wherein, each input read register bit is capable of reflecting a state signal associated with an external binary state device coupled to the input read register bit, and each output drive register bit is capable of reflecting a state signal associated with an external binary state device coupled to the output drive register bit and is further capable of altering the state signal associated with the external binary state device coupled to the output drive register; and further wherein the memory device is capable of modifying the state of the external binary state device coupled to each controlled register bit by providing a path from the external binary state device to each controlled register bit to an output supply voltage or ground coupled to the memory device.

2. The device of claim 1 , wherein the memory device further comprises a first bit that is fixed as an input read register bit and a second bit that is fixed as an output drive register bit.

3. The device of claim 1 , wherein each controlling bit corresponds to a set of one or more controlled bits, and each controlling bit is used to determine whether the corresponding controlled bits are associated with the output drive register or input read register.

4. The device of claim 1 , wherein the controlling bits, taken together, define states that indicate which of the controlled bits are associated with the output drive register and which are associated with the input read register.

5. The device of claim 1 , further comprising one or more ports, where each port is capable of interfacing with external read/write signals and each port is coupled to the controlled register bits.

6. The device of claim 5 , wherein each port is capable of reading values from each input read register bit and each port is capable of writing values to each output drive register bit.

7. The device of claim 1 , wherein the controlling bits are defined dynamically based on an input signal.

8. The device of claim 1 , wherein the controlling bits each correspond to a pin on a chip.

9. The device of claim 1 , wherein the controlling bits are set at startup.

10. The device of claim 1 , wherein the controlled register bits each correspond to a pin on a chip.

11. The memory device of claim 1 having a special function decode module coupled to the input read register and the output drive register.

12. The memory device of claim 11 wherein the special function decode module determines which controlled bits are coupled to the input read register and which controlled bits are coupled to the output drive register, based on one or more controlling bits.

13. A memory device, comprising: one or more ports, each port capable of interfacing with external read/write signals; an input read register coupled to the one or more ports and to a first set of external binary state devices, the input read register associated with a first memory address; an output drive register coupled to the one or more ports and to a second set of external binary state devices, the output drive register associated with a second memory address; one or more controlling bits, wherein each controlling bit is capable of being set; and a set of controlled register bits, wherein the set of controlled register bits comprise a first set of bits and a second set of bits and setting the one or more controlling bits defines which controlled register bits are in the first set of bits and which are in the second set of bits; and wherein, the input read register includes the first set of bits, and the first set of bits are capable of reflecting a first set of state signals associated with the first set of external binary state devices, and the output drive register includes the second set of bits, and the second set of bits are capable of reflecting a second set of state signals associated with the second set of external binary state devices and are further capable of altering the second set of state signals associated with the second set of external binary state devices; and further wherein the memory device is capable of modifying the state of the external binary state device coupled to each controlled register bit by providing a path from the external binary state device to each controlled register bit to an output supply voltage or ground coupled to the memory device.

14. A memory device, comprising: one or more ports, each port capable of interfacing with external read/write signals; one or more controlling bits, wherein each controlling bit is capable of being set; and a set of controlled register bits, wherein setting the one or more controlling bits defines a set of bits of the set of controlled register bits to associate with an input read register; and the input read register coupled to the one or more ports and to a set of external binary state devices, each external binary state device of the set of external binary state devices being located external to the memory device, wherein the input read register is associated with a memory address, wherein the set of bits are capable of reflecting a set of state signals associated with the set of external binary state devices at the memory address; and further wherein the memory device is capable of modifying the state of the external binary state device coupled to each controlled register bit by providing a path from the external binary state device to each controlled register bit to an output supply voltage or ground coupled to the memory device.

15. A memory device, comprising: one or more ports, each port capable of interfacing with external read/write signals; one or more controlling bits, wherein each controlling bit is capable of being set; and a set of controlled register bits, wherein setting the one or more controlling bits defines a set of bits of the one or more controlled register bits to associate with an output drive register; and the output drive register coupled to the one or more ports and to a set of external binary state devices, each external binary state device of the set of external binary state devices being located external to the memory device, the output drive register associated with a memory address, wherein the set of bits are capable of altering a set of state signals associated with the set of external binary state devices via the memory address and further wherein the memory device is capable of modifying the state of the external binary state device coupled to each controlled register bit by providing a path from the external binary state device to each controlled register bit to an output supply voltage or ground coupled to the memory device.

16. A method for controlling states of a plurality of external binary state devices coupled to a memory device, each external binary state device of the external binary state devices being located external to the memory device, the method comprising the steps of: coupling one or more processors to the memory device; setting one or more controlling bits; using a special function decode module coupled to an input read register (IRR) and an output driver register (ODR) to determine, based on the one or more controlling bits, at least one bit from a set of controlled register bits for reflecting a state of at least one of the plurality of external binary state devices; reading, using the one or more processors, to a first memory location of the memory device, wherein the first memory location corresponds to the one or more bits that reflect the state of the at least one of the plurality of external binary state devices; and controlling the states of the external binary state device by providing a path from the plurality of external binary state devices to an output supply voltage or ground coupled to the memory device.

17. A method for controlling states of a plurality of external binary state devices coupled to a memory device, each external binary state device of the external binary state devices being located external to the memory device, the method comprising the steps of: coupling one or more processors to the memory device; setting one or more controlling bits; using a special function decode module coupled to an input read register (IRR) and an output driver register (ODR) to determine, based on the one or more controlling bits, at least one bit from a set of controlled register bits for controlling the change of a state of one or more of the plurality of external binary state devices; and writing, using the one or more processors, to a memory location of the memory device, wherein the memory location corresponds to the one or more bits that control the change of state of the one or more of the plurality of external binary state devices; and controlling the states of the external binary state device by providing a path from the plurality of external binary state devices to an output supply voltage or ground coupled to the memory device.

18. A method for controlling states of a plurality of external binary state devices coupled to a memory device, each external binary state device of the external binary state devices being located external to the memory device, the method comprising: coupling one or more processors to the memory device; setting one or more controlling bits; using a special function decode module coupled to an input read register (IRR) and an output driver register (ODR) to determine, based on the one or more controlling bits, a first set of one or more bits from a set of controlled register bits for reflecting a first state of a first one of the plurality of external binary state devices and a second set of one or more bits from the set of controlled register bits for controlling the change of a state of a second one of the plurality of external binary state devices; and monitoring the first state of the first one of the plurality of external binary state devices using the first set of one or more bits; and manipulating the second state of the second one of the plurality of external binary state devices using the second set of one or more by providing a path from the plurality of external binary state devices to an output supply voltage or ground coupled to the memory device.

19. A system for controlling and monitoring one or more external binary state devices, the system comprising: a multi-port memory device that includes a memory array, an input read register and an output drive register, each coupled to a plurality of ports of the multi-port memory device; a plurality of processors coupled to the plurality of ports, wherein each processor is capable of executing an instruction that reads to a first memory address of the multi-port memory device, and reads and writes to a second memory address of the multi-port memory device; one or more controlling bits, wherein each controlling bit is capable of being set; and a set of controlled register bits, wherein setting the one or more controlling bits defines which controlled register bits are associated with the input read register and which are associated with the output drive register; and wherein the input read register is associated with the first memory address and is coupled to a first set of the one or more external binary state devices, and the output drive register associated with the second memory address and is coupled to a second set of the one or more external binary state devices; and further wherein the memory device is capable of modifying the state of the external binary state device coupled to each controlled register bit by providing a path from the external binary state device to each controlled register bit to an output supply voltage or ground coupled to the memory device.

20. A system for controlling and monitoring one or more binary state devices, the system comprising: a multi-port memory device that includes a memory array and a register, each coupled to a plurality of ports of the multi-port memory device; a plurality of processors coupled to the plurality of posts, wherein each processor is capable of executing an instruction that reads and writes to a memory address of the multi-post memory device; one or more controlling bits, wherein each controlling bit is capable of being set; and a set of controlled register bits associated with the register, wherein setting the one or more controlling bits defines which controlled register bits are associated with the memory address, and wherein the register is coupled to a set of the one or more binary state devices; and further wherein the memory device is capable of modifying the state of the external binary state device coupled to each controlled register bit by providing a path from the external binary state device to each controlled register bit to an output supply voltage or ground coupled to the memory device.