Semiconductor Device, a Parallel Interface System and Methods Thereof

1. A semiconductor device included within a parallel interface system, comprising: a reference clock transmitting block generating a reference clock signal; a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals; and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate phase-controlled sampling clock signals for the respective plurality of first transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode, wherein the per-pin deskew block, enables one of the plurality of training data bit signals to be transmitted to a receiving semiconductor device in synchronization with a corresponding phase controlled transmitting sampling clock signal, receives the training data bit signals back from the receiving semiconductor device in synchronization with a given receiving sampling clock signal, and outputs a plurality of control signals for respectively controlling the phases of the phase-controlled transmitting sampling clock signals respectively corresponding to the plurality of training data bit signals based on a comparison between the transmitted training data bit signals and the received training data bit signals.

2. The semiconductor device of claim 1 , wherein the phase skew information is transmitted from a receiving semiconductor device to one of the plurality of first transceiver blocks via a data line.

3. The semiconductor device of claim 1 , wherein each of the plurality of first transceiver blocks includes: a delay locked loop block controlling the phase of a given phase-controlled transmitting sampling clock signal based on one of a given control signal and the phase skew information; a driver outputting data in synchronization with the given phase-controlled transmitting sampling clock signal; and a clock and data recovery (CDR) reception block receiving one of data and the phase skew information.

4. The semiconductor device of claim 3 , further comprising: a plurality of selectors, each of the plurality of selectors selecting one of the given control signal and the phase skew information received by the corresponding clock and data recovery reception block in response to a mode control signal and outputting the selection to the delay locked loop block.

5. The semiconductor device of claim 1 , further comprising: at least one phase information receiver receiving the phase skew information from a receiving semiconductor device through at least one phase information transmission line.

6. The semiconductor device of claim 5 , wherein each of the plurality of first transceiver blocks includes: a delay locked loop block controlling the phase of a given phase-controlled transmitting sampling clock signal based on one of a given control signal and the phase skew information; a driver outputting data in synchronization with the given phase-controlled transmitting sampling clock signal; and a clock and data recovery reception block receiving data.

7. The semiconductor device of claim 6 , further comprising: a plurality of selectors, each of the plurality of selectors selecting one of the given control signal and the phase skew information received by the phase information receiver in response to a mode control signal and outputting the selection to the delay locked loop block.

8. A parallel interface system, comprising; a first semiconductor device configured as the semiconductor device of claim 1 , the phase skew information being received at the first semiconductor device from a second semiconductor device; a plurality of connections between the first and second semiconductor devices; the second semiconductor device including a reference clock receiving block receiving the reference clock signal and outputting at least two first receiving sampling clock signals having different phases based on the received reference clock signal, a plurality of second transceiver blocks transferring the plurality of parallel data bit signals to/from the plurality of first transceiver blocks, respectively, via one or more of the plurality of connections; and a phase detector for detecting the phase skew information.

9. The parallel interface system of claim 8 , wherein the second semiconductor device further comprises: a phase statistics block transmitting, to the first semiconductor device, phase information calculated based on the phase skew information detected by the phase detector during a given period, the phase of the phase-controlled transmitting sampling clock signals being controlled based at least in part on the calculated phase information.

10. The parallel interface system of claim 9 , wherein the second semiconductor device further comprises: a selector transmitting the calculated phase information to one of the plurality of second transceiver blocks in response to a control command received from the first semiconductor device, at least one of the plurality of second transceiver blocks transmitting the calculated phase information to a corresponding first transceiver block among the plurality of first transceiver blocks.

11. The parallel interface system of claim 9 , wherein the second semiconductor device includes a phase information transmitter for transmitting the calculated phase information and the first semiconductor device includes a phase information receiver for receiving the calculated phase information transmitted by the phase information transmitter.

12. A method of for reducing skew between a reference clock signal and each of a plurality of parallel data bit signals in a parallel interface system including a plurality of transceiver blocks, comprising: first mode adjusting a phase of a sampling clock signal to generate a phase-controlled sampling clock signal based on a phase skew between a training data bit signal, among a plurality of training data bit signals, corresponding to a given transceiver block and a reference clock signal in a first operation mode; and second mode adjusting the phase of the sampling clock signal to generate the phase-controlled sampling clock signal based on phase skew information relating to a phase skew between a given data bit signal and the reference clock signal in a second operation mode, wherein the sampling clock signal is a transmitting sampling clock signal, the first mode adjusting step includes, transmitting a plurality of training data bit signals to a receiving semiconductor device in synchronization with the transmitting sampling clock signal, and receiving the plurality of training data bit signals back from the receiving semiconductor device in synchronization with a given receiving sampling clock signal, and the first mode adjusting step further adjusts the phase of the transmitting sampling clock signal for each of the plurality of transceiver blocks based on a comparison between the transmitted plurality of training data bit signals and the received plurality of training data bit signals.

13. The method of claim 12 , wherein, the transmitting sampling clock signal has a given frequency, the receiving sampling clock signal has different phase values respectively for each of the plurality of training data bit signals, and wherein the first mode adjusting step further adjusts the phases of the receiving sampling clock signal based on a comparison between the transmitted plurality of training data bit signals and the received plurality of training data bit signals.

14. The method of claim 12 , wherein the second mode adjusting step includes: receiving the phase skew information from a receiving semiconductor device via one of the plurality of transceiver blocks.

15. The method of claim 12 , wherein the second mode adjusting step includes: receiving the phase skew information from a receiving semiconductor device via a phase information receiver.

16. The method of claim 12 , wherein the transmitting sampling clock signal is a first of two transmitting sampling clock signals, each phase-controlled first transmitting sampling clock signal corresponding to one of the plurality of parallel data bit signals.

17. The method of claim 16 , wherein the second mode adjusting step includes: transmitting the reference clock signal and the plurality of parallel data bit signals, which are transmitted in synchronization with the first transmitting sampling clock signal, from a first semiconductor device to a second semiconductor device; and detecting, at the second semiconductor device, the phase skew information; and transmitting the phase skew information from the second semiconductor device to the first semiconductor device.

18. The method of claim 17 , wherein the detecting step includes: generating a plurality of receiving sampling clock signals, each of the receiving sampling clock signals having different phases based on the reference clock signal; and detecting the phase skew information based on a result of sampling at least one data bit signal among the plurality of parallel data bit signals in synchronization with the plurality of receiving sampling clock signals.

19. The method of claim 18 , wherein the detecting step further includes: sampling the at least one data bit signal based on the receiving sampling clock signals, a first of the plurality of receiving sampling clock signals being in phase with the reference clock signal and a second of the receiving sampling clock signals having a half-period phase difference with the reference clock signal.

20. The method of claim 18 , wherein the transmitting the phase skew information step includes: transmitting the phase skew information to the first semiconductor device through a data line corresponding to the sampled at least one data bit signal in response to a control command received from the first semiconductor device.

21. The method of claim 18 , wherein the transmitting the phase skew information step includes: transmitting the phase skew information to the first semiconductor device through a phase information transmission line.