Legal claims defining the scope of protection, as filed with the USPTO.
1. An in-circuit debugging (ICD) system, comprising: at least a first target processor having an embedded debug module (EDM), where the first target processor performs a program code in a normal mode and the first EDM controls the first target processor in a debug mode; a debug information memory (DIM), for storing debug information for debugging in the debug mode, wherein the DIM is invisible to the first target processor when the first target processor operates in the normal mode; a debug host having a debug software, for debugging the program code by using the debug information in the debug mode; and an in-circuit debugging bridge (ICD bridge) having a host debug module (HDM) coupled to the first EDM, the ICD bridge being coupled between the first target processor and the debug host and utilized for bridging information communicated between the first target processor and the debug host.
2. The ICD system of claim 1 , further comprising: a target system memory affixed to the first target processor, for storing the program code in the normal mode, wherein a portion of a processor address space in the debug mode is allocated to the DIM, and the portion of the processor address space is remapped back to the target system memory when the debug mode exits.
3. The ICD system of claim 1 , wherein the DIM is mapped to a physical address space visible to the first target processor, and the DIM is only used for instruction fetching.
4. The ICD system of claim 1 , wherein the DIM is mapped to a physical address space visible to the first target processor, and the DIM is used for instruction fetching and data access.
5. The ICD system of claim 1 , wherein the DIM is mapped to a virtual address space visible to the first target processor, and the debug software directly uses information accessible through the virtual address space or debug user space program code without additional translation.
6. The ICD system of claim 1 , further comprising: one or more second target processors, each having a second EDM, coupled to the first target processor and the HDM through an ICD chain, for performing a code segment of the program code in the normal mode, the second EDM of each second target processor being utilized for controlling the second target processor in the debug mode; wherein the first and second target processors form an ICD chain; and when the first target processor is trapped into the debug mode, the first target processor transmits a notification to one or more of the second target processors to trap the second target processors into the debug mode.
7. The ICD system of claim 6 , wherein the debug host transmits the notification to the first target processor to trap the first target processor into the debug mode.
8. The ICD system of claim 6 , wherein the first target processor transmits the notification to the debug host when entering the debug mode, requesting a debug instruction in the debug mode, or being utilized for data transfer between the first target processor and the debug host.
9. The ICD system of claim 1 , wherein the debug host initiates a data transfer between the HDM of the ICD bridge and the EDM of the first target processor for transmitting information to a target system memory affixed to the first target processor, and the information includes a specific suffix bit pattern used for determining whether the information transmitted by the debug host is received by the first target processor.
10. The ICD system of claim 9 , wherein the EDM of the first target processor changes content of the specific suffix bit pattern and then returns the specific suffix bit pattern to the HDM when the information transmitted by the debug host is successfully received by the first target processor.
11. The ICD system of claim 9 , wherein the information transmitted by the debug host is a block of data used for updating at least a portion of the target system memory.
12. The ICD system of claim 1 , wherein the first target processor further comprises at least one debug register, and the debug register is read-only to the first target processor in debug mode.
13. An in-circuit debugging (ICD) method, comprising: providing at least a first target processor having an embedded debug module (EDM) and an address translation function that translates between physical address and virtual address, where the first target processor performs a program code in a normal mode, and using the first EDM to control the first target processor in a debug mode; providing a debug information memory (DIM) to store debug information for debugging in the debug mode, wherein the DIM is invisible to the first target processor when the first target processor operates in the normal mode; utilizing a debug software of a debug host to debug the program code by using the debug information in the debug mode; and bridging information communicated between the first target processor and the debug host.
14. The ICD method of claim 13 , further comprising: providing a target system memory for storing the program code in the normal mode, wherein a portion of a processor address space in the debug mode is allocated to the DIM, and the portion of the processor address space is remapped back to the target system memory when the debug mode exits.
15. The ICD method of claim 13 , further comprising: mapping the DIM to a physical address space visible to the first target processor, wherein the DIM is only used for instruction fetching.
16. The ICD method of claim 13 , further comprising: mapping the DIM to a physical address space visible to the first target processor, wherein the DIM is used for instruction fetching and data access.
17. The ICD method of claim 13 , further comprising: mapping the DIM to a virtual address space visible to the first target processor; and directly using information accessible though the virtual address space or debug user space program code without additional translation.
18. The ICD method of claim 13 , further comprising: providing one or more second target processors each having a second EDM, wherein each second target processor performs a code segment of the program code in the normal mode, the second EDM of each second target processor controls the second target processor in the debug mode, and the first and second target processors are coupled through an ICD chain; and using the first target processor to transmit a notification to one or more of the second target processors to trap the second target processors into the debug mode when the first target processor is trapped into the debug mode.
19. The ICD method of claim 18 , further comprising: utilizing the debug host to transmit the notification to the first target processor to trap the first target processor into the debug mode.
20. The ICD method of claim 18 , further comprising: utilizing the first target processor to transmit the notification to the debug host when entering the debug mode, requesting a debug instruction in the debug mode, or being utilized for data transfer between the first target processor and the debug host.
21. The ICD method of claim 13 , further comprising: initiating a data transfer between an HDM of an ICD bridge and the EDM of the first target processor for transmitting information to a target system memory affixed to the first target processor where the information includes a specific suffix bit pattern used for determining whether the information transmitted by the debug host is received by the first target processor.
22. The ICD method of claim 21 , further comprising: changing content of the specific suffix bit pattern and then returning the specific suffix bit pattern to the HDM when the information transmitted by the debug host is successfully received by the first target processor.
23. The ICD method of claim 21 , wherein the information transmitted by the debug host is a block of data used for updating at least a portion of the target system memory.
24. The ICD method of claim 13 , wherein the first target processor further includes at least one debug register and the debug register is read-only to the first target processor in the debug mode.
Unknown
March 22, 2011
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.