Voltage Indicator Signal Generation System and Method

1. A method, comprising: receiving an asserted system reset signal; generating a peripheral component interconnect (PCI) bus reset signal based on the received system reset signal; determining a PCI operational mode of a PCI bus; and stabilizing a voltage indicator signal based on the determined PCI operational mode prior to a deassertion of the system reset signal.

2. The method as recited in claim 1 , wherein determining a PCI operational mode of a PCI bus comprises: sampling a PCIXCAP signal.

3. The method as recited in claim 1 , further comprising: generating a PCI clock signal; and generating initialization commands for devices coupled to the PCI bus.

4. The method as recited in claim 1 , wherein the system reset signal is a power-on reset (POR) signal.

5. A computer program product, the computer program product having a medium with a computer program embodied thereon, the computer program comprising: computer code for receiving a system reset signal; computer code for generating a peripheral component interconnect (PCI) bus reset signal based on the received system reset signal; computer code for determining a PCI operational mode of a PCI bus; and computer code for stabilizing a voltage indicator signal based on the determined PCI operational mode prior to a deassertion of the system reset signal.

6. The computer program product as recited in claim 5 , wherein computer code for determining a PCI operational mode of a PCI bus comprises: computer code for sampling a PCIXCAP signal.

7. The computer program product as recited in claim 5 , further comprising: computer code for generating a PCI clock signal; and computer code for generating initialization commands for devices coupled to the PCI bus.

8. The computer program product as recited in claim 5 , wherein the system reset signal is a power-on reset (POR) signal.

9. The method as recited in claim 1 , wherein the system reset signal is deasserted based on a predetermined power-on reset (POR) settling time, and wherein the predetermined POR settling time comprises a system reference clock stabilization time and a system reference voltage stabilization time.

10. The computer program product as recited in claim 5 , wherein the system reset signal is deasserted based on a predetermined power-on reset (POR) settling time, and wherein the predetermined POR settling time comprises a system reference clock stabilization time and a system reference voltage stabilization time.