Method and Apparatus for Designing a Three-Dimensional Integrated Circuit

1. A method of designing a three-dimensional integrated circuit, comprising: designating, in a computer, a plurality of partition lines dividing two-dimensional layout data of a circuit to be formed on a semiconductor substrate into a plurality of layout block data in order to re-arrange in different layers, each of the plurality of layout block data including data of a semiconductor circuit; generating, in the computer, reversed layout block data reversing of one of two layout block data adjacent to each other among the plurality of layout block data by reversing the one of the layout data symmetrically with respect to a specified partition line among the plurality of partition lines; arranging, in the computer, the reversed layout block data and the other of the two block layout data to form two layers vertically stacked assuming with the semiconductor substrate interposed therebetween; selecting, in the computer, at least one pair of interconnects included in a the two layout block data of the circuit, ranging over the two layers, and mutually and functionally relating, with respect to at least one of time delay, interconnect length and block configuration; and re-arranging, in the computer, the at least one pair of interconnects selected using a via connecting an upper one and an under one of the interconnects.

2. The method according to claim 1 , wherein said re-arranging the at least one pair of interconnects selected using the via includes setting a total length of the interconnects after re-arrangement to be short as compared with an interconnect length on an original two-dimensional layout drawing.

3. The method according to claim 1 , wherein said re-arranging the at least one pair of interconnects selected using the via includes setting a total length of the interconnects to be short as compared with an interconnect length of an original two-dimensional layout drawing.

4. The method according to claim 1 , wherein said re-arranging the at least one pair of interconnects selected using the via includes arranging an original two-dimensional layout drawing so as to partially overlap between the two layers stacked.

5. The method according to claim 1 , wherein said designating a plurality of partition lines dividing two-dimensional layout data includes designating a partition line along a global interconnect portion shared by a plurality of layout blocks corresponding to the layout block data.

6. The method according to claim 1 , wherein said designating a plurality of partition lines dividing two-dimensional layout data includes dividing and classifying the two-dimensional layout data in accordance with a circuit function to designate the partition lines.

7. The method according to claim 1 , wherein said designating a plurality of partition lines dividing two-dimensional layout data includes leaving an internal interconnect in one of the layout block data without ranging over the plurality of layout block data.

8. The method according to claim 1 , wherein the semiconductor circuit includes at least one circuit selected from the group consisting of a logic circuit, a radio-frequency (RF) circuit, a random-access-memory (RAM) circuit, an analogue circuit, an application-specific integrated circuit (ASIC), a CPU, and a flash memory.

9. An apparatus for designing a three-dimensional integrated circuit, comprising: a block dividing part dividing two-dimensional layout data of a circuit to be formed on a semiconductor substrate into a plurality of layout block data in order to re-arrange in different layers, each of the layout block data including a semiconductor circuit; a reverse data generation part generating reverse layout block data by reversing one of the two layout block data among the plurality of layout block data symmetrically with respect to a specified partition line; a three-dimensional layout generation part alternately stacking the plurality of layout block data divided by the block dividing part and the reverse layout block data generated by the reverse data generation part to a plurality of vertically overlapped layers; and a re-arrangement part selecting at least one pair of interconnects which are included in a plurality of layout block data of the circuit, range over plural layers, and so as to mutually and functionally relate with respect to at least one of time delay, interconnect length and block configuration, and short-circuiting the pair of interconnects selected using a via connecting an upper one and an under one of the selected interconnects.

10. The apparatus according to claim 9 , wherein the re-arrangement part sets a length of the interconnect after re-arrangement to be short as compared with an interconnect length of an original two-dimensional layout drawing.

11. The apparatus according to claim 9 , wherein the rearrangement part sets an effective length of the interconnect to be short as compared with an original two-dimensional layout drawing.

12. The apparatus according to claim 9 , wherein the rearrangement part arranges part of an original two-dimensional layout drawing to overlap between the two layers stacked.

13. The apparatus according to claim 9 , wherein the block dividing part divides the layout block data along a global interconnect portion shared by a plurality of layout blocks corresponding to the layout block data.

14. The apparatus according to claim 9 , wherein the block dividing part divides and classifies the layout block data in accordance with a circuit function.

15. The apparatus according to claim 9 , wherein the block dividing part divides an internal interconnect in the layout block without ranging over a plurality of layout blocks.

16. The apparatus according to claim 9 , wherein the semiconductor circuit includes at least one circuit selected from the group consisting of a logic circuit, a radio-frequency (RF) circuit, a random-access-memory (RAM) circuit, an analogue circuit, an application-specific integrated circuit (ASIC), a CPU, and a flash memory.