SSD with Sata and USB Interfaces

1. A data storage system, comprising: a plurality of solid state memory devices each including at least one memory unit; and a controller coupled to the plurality of solid state memory devices, the controller including: a data interface of a first type and a data interface of a second type, each of the data interfaces of the first and second types configured to be coupled to a corresponding data interface of a host device, a first serial data bus coupled to each of the data interfaces of the first and second types and to each of the plurality of the solid state memory devices, a plurality of processors of a first type, each of the plurality of processors of the first type coupled to a respective solid state memory device, and a processor of a second type configured to manage access to the first serial data bus by the plurality of processors of the first type, the controller configured to manage data flow between the plurality of solid state memory devices and the host device through the data interfaces of the first and second types.

2. The data storage system of claim 1 , wherein the controller includes a multiplexer configured to combine data received from the data interfaces of the first and second types and provide the combined data to the first serial data bus.

3. The data storage system of claim 2 , wherein the multiplexer is configured to distribute data received from the plurality of solid state memory devices between the data interfaces of the first and second types.

4. The data storage system of claim 1 , wherein the data interface of the first type is a serial advanced technology attachment (SATA) interface, and the data interface of the second type is a universal serial bus (USB) interface.

5. The data storage system of claim 1 , wherein the first serial data bus is a serial advanced technology attachment (SATA) channel.

6. The data storage system of claim 1 , wherein the first serial data bus is a universal serial bus (USB) channel.

7. The data storage system of claim 1 , wherein each of the plurality of processors of the first type are configured to perform wear-leveling for the solid state memory device to which it is coupled.

8. An integrated circuit chip, comprising: a first data port disposed on the integrated circuit chip and configured to be coupled to a serial data channel of a first type; a second data port disposed on the integrated circuit chip and configured to be coupled to a serial data channel of a second type; a plurality of memory ports disposed on the integrated circuit chip, each of the plurality memory ports configured to be coupled to a respective memory device; a data channel disposed on the integrated circuit chip and coupled to the first and second data ports and to the one or more memory ports; and a controller disposed on the integrated circuit chip and configured to manage data flow between the one or more memory ports and the first and second data ports, the controller including a number of processors of a first type equal to a number of the memory ports, each of the processors of the first type associated with a respective one of the plurality of memory ports, and a processor of a second type for managing access to the data channel by each of the processors of the first type.

9. The integrated circuit of claim 8 , wherein the serial data bus of the first type is a serial advanced technology attachment (SATA) channel.

10. The integrated circuit of claim 9 , wherein the serial data channel of the second type is a universal serial bus (USB) channel.

11. The integrated circuit of claim 8 , wherein the data channel includes a first-in first-out register (FIFO).

12. The integrated circuit of claim 8 , wherein the data channel is a serial advanced technology attachment (SATA) channel.

13. The integrated circuit of claim 8 , wherein each of the processors of the first type are configured to execute an error correction code on data being transferred to a respective memory port.

14. The integrated circuit of claim 8 , wherein the controller includes: a multiplexer (mux) disposed between the data channel and the first and second data ports, the mux configured to combine data received from the first and second data ports and transmit it to the data channel.

15. The integrated circuit of claim 14 , wherein the multiplexer is configured to receive data from the data channel and distribute it to the first and second data ports.

16. A solid state drive (SSD), comprising: a first data port configured to be coupled to a serial data bus of a first type; a second data port configured to be coupled to a serial data bus of a second type; a multiplexer (mux) coupled to the first and second data ports and a data channel, the mux configured to route data received from the data channel to the first and second data ports; a plurality of processors of a first type coupled to the data channel, each of the plurality of processors configured to be coupled to a respective group of flash memory; and a processor of a second type coupled to each of the plurality of processors of the first type and to the mux, the processor of the second type configured to manage data flow from the groups of flash memory to the first and second data ports.

17. The SSD of claim 16 , wherein the serial data port of the first type is a serial advanced technology attachment (SATA) channel, and the serial data port of the second type is a universal serial bus (USB) channel.

18. The SSD of claim 16 , wherein each of the plurality of processors of the first type are configured to perform wear-leveling operations for its respective group of flash memory.

19. The SSD of claim 16 , wherein each of the plurality of processors of the first type are configured to execute an error correction coding on data being transferred from its respective group of flash memory.

20. The SSD of claim 16 , wherein at least one of the groups of flash memory includes single-level cell flash.

21. The SSD of claim 20 , wherein at least one of the groups of flash memory includes multi-level cell flash.

22. The SSD of claim 16 , wherein at least one of the groups of flash memory includes multi-level cell flash.

23. The SSD of claim 16 , wherein at least one of the groups of flash memory includes a combination of multi-level cell (MLC) flash and single-level cell (SLC) flash.