Two-Wire Serial Handshaking Communication Interface and Method Thereof

1. A communication interface for transmitting a data bit representative between a first transmitting component and a second transmitting component, the communication interface comprising: a first input/output unit contained in the first transmitting component having a first input mode for detecting a level of a first signal and a first output mode for inverting the level of the first signal; a second input/output unit contained in the second transmitting component having a second input mode for detecting the level of the first signal and a second output mode for inverting the level of the first signal, wherein the second input/output unit is electrically connected to the first input/output unit for transmitting the first signal; a third input/output unit contained in the second transmitting component having a third input mode for detecting a level of a second signal and a third output mode for inverting the level of the second signal; and a fourth input/output unit contained in the first transmitting component having a fourth input mode for detecting the level of the second signal and a fourth output mode for inverting the level of the second signal, wherein the fourth input/output unit is electrically connected to the third input/output unit for transmitting the second signal; wherein the first input/output unit and the second input/output unit constitute a first circuitry, the fourth input/output unit and the third input/output unit constitute a second circuitry, and each of the first and the second circuitries is configured as one of a “wired-and” logic circuitry and a “wired-or” logic circuitry and generates the first signal and the second signal having a first level value in advance, wherein the data bit representative has a complete transmission procedure that initiates in a subordinate idle state followed by four level changes in a subordinate data state process, a subordinate receiver acknowledge state process, a subordinate transmitter acknowledge state process and the subordinate idle state process sequentially, wherein in the subordinate data state process, one of a relatively high state data bit representative and a relatively low state data bit representative is selected as the data bit representative by the levels of the first signal and the second signal; wherein the first and the second circuitries respectively further comprise a first transmitting line and a second transmitting line for serving as transmitting channels, wherein the first transmitting line is electrically connected to a first terminal of a first unit having a second terminal electrically connected to one of a power potential and a ground potential, the second transmitting line is electrically connected to a third terminal of a second unit having a fourth terminal electrically connected to one of the power potential and the ground potential for forming both the first and the second circuitries as one of the “wired-and” and the “wired-or” logic circuitry so as to generate the respective first level value as one of a high and a low level values for the first and second signals; and wherein each of the first input/output unit, the second input/output unit, the third input/output unit and the fourth input/output unit comprises: an input buffer receiving the first signal when electrically connected to the first transmitting line and receiving the second signal when electrically connected to the second transmitting line; and a transistor being one of an N-channel metal oxide semiconductor field effect transistor when the first and the second circuitries are the “wired-and” logic circuitry and a P-channel metal oxide semiconductor field effect transistor when the first and the second circuitries are the “wired-or” logic circuitry, and having a drain electrically connected to the input buffer, a source electrically connected to one of a ground potential when the first and the second circuitries are the “wired-and” logic circuitry and a power potential when the first and the second circuitries are the “wired-or” logic circuitry, and a gate for receiving a selective level, so that each of the input/output units is initially configured as the input mode thereof and the first and the second signals with the first level value are generated for generating a respective second level value during the output mode of each of the input/output units.

2. A communication interface as claimed in claim 1 , wherein when the first signal and the second signal are initially configured to have the first level value, the level of the second signal is detected by the fourth input/output unit and the level of the first signal is detected by the second input/output unit, wherein for transmitting the data bit representative from the first transmitting component to the second transmitting component, the first signal is inverted by the first input/output unit to a second level value for initiating the transmission of the data bit representative and the second signal is inverted by the third input/output unit to the first level value for completing the transmission of the data bit representative, and for transmitting the data bit representative from the second transmitting component to the first transmitting component, the second signal is inverted by the third input/output unit to the second level value for initiating the transmission of the data bit representative and the first signal is inverted by the first input/output unit to the first level value for completing the transmission of the data bit representative.

3. A communication interface as claimed in claim 1 , wherein the first transmitting component transmits a plurality of the data bit representatives to the second transmitting component for performing a batch of a serial transmission.

4. A method for a two-wire serial handshaking communication for a transmission of a data bit representative between a first transmitting component and a second transmitting component, wherein the first transmitting component comprises a first input/output unit and a second input/output unit and the second transmitting component comprises a third input/output unit and a fourth input/output unit, wherein the first input/output unit and the second input/output unit transmit a first signal through a first transmitting line electrically connected therebetween and the third input/output unit and the fourth input/output unit transmit a second signal transmitted through a second transmitting line electrically connected therebetween, the method comprising steps of: (a) configuring the first signal and the second signal with a respective first level value being one of a relatively high level value and a relatively low level value in a subordinate idle state process; (b) configuring one of the first transmitting component and the second transmitting component as an output component and the other thereof as a receiving component, wherein one of the two input/out units of the output component is configured as a transmission-initiating input/output unit for generating a first inversion of one of a level of the first and a level of the second signals for initiating the transmission of the data bit representative in a subordinate data state process; (c) defining the data bit representative as one of a relatively high state data bit representative and a relatively low state data bit representative based on the levels of the first signal and the second signal after the first inversion are detected by one of the two input/output units in the receiving component as a first related input/output unit related to the first critical inversion in a first non-busy time; (d) generating a second inversion of the other of the levels of the first and the second signals in a subordinate receiver acknowledge state process by the other of the two input/output units in the receiving component as a second related input/output unit; (e) re-initiating the transmission-initiating input/output unit and generating a third inversion of the one of the level of the first and the second signals in a subordinate transmitter acknowledge state process after the second inversion is detected by the other of the two input/output units in the output component as a third related input/output unit in a second non-busy time; (f) re-initiating the second related input/output unit for generating a fourth inversion of the other of the levels of the first and the second signals in the subordinate idle state process for completing the data bit representative transmission after the third inversion is detected by the first related input/output component in the receiving component in a third non-busy time; and (g) managing a transmission of another data bit representative to be initiated in one output component selected from one of the first transmitting component and the second transmitting component in a fourth non-busy time.

5. A method as claimed in claim 4 , wherein the step (a) comprises a step of: starting input modes of the first, the second, the third and the fourth input/output units in advance, wherein the levels of the first and second signals are detected.

6. A method as claimed in claim 4 , wherein the step (b) comprises a step of: configuring the levels of the first and the second signals inverse to each other for defining the data bit representative as one of the relatively high state data bit representative and the relatively low state data bit representative, wherein the high state data bit representative is expressed as a relatively high bit state and the low state data bit representative is expressed as a relatively low bit state.

7. A method as claimed in claim 4 , wherein the step (b) comprises a step of: defining the data bit representative as the relatively high state data bit representative when the first signal has the relatively high level and the second signal has the relatively low level, and defining the data bit representative as the relatively low state data bit representative when the first signal has the relatively low level and the second signal has the relatively high level.

8. A method as claimed in claim 4 , wherein when the transmission of the data bit representative is transmitted from the first transmitting component to the second transmitting component, the steps (b)-(f) are performed by steps of: initiating an output mode of the first input/output unit and generating the first inversion for the first signal for initiating the transmission of the data bit representative when the first level values of the first and the second signals are respectively detected by the first and the second input/output units; defining the data bit representative as the one of the relatively high state data bit representative and the relatively low state data bit representative based on levels of the first signal and the second signal after the first inversion is detected by the third input/output unit in the second transmitting component in the first non-busy time; starting an output mode of the fourth input/output unit and generating the second inversion of the second signal; re-initiating an input mode of the first input/output unit for generating the third inversion for the first signal after the second inversion is detected by the second input/output unit in the first transmitting component in a second spare time; re-initiating an input mode of the fourth input/output unit for generating the fourth inversion for the second signal for transmitting the data bit representative completely after the third inversion is detected by the third input/output unit in the second transmitting component in the third spare time; and managing a transmission of another data bit representative to be initiated in one of the first transmitting component and the second transmitting component in the fourth spare time.

9. A method as claimed in claim 4 , wherein when the transmission of the data bit representative is transmitted from the first transmitting component to the second transmitting component, the steps (b)-(f) are performed by steps of: initiating an output mode of the second input/output unit, generating the first inversion for the second signal and initiating the transmission of the data bit representative when the first levels of the first and the second signals are respectively detected by the first and the second input/output units; defining the data bit representative as the one of the relatively high state data bit representative and the relatively low state data bit representative based on the levels of the first signal and the second signal when changes of the levels after the first inversion is detected by the fourth input/output unit in the second transmitting component in the first spare time; starting an output mode of the third input/output unit and generating the second inversion of the first signal; re-initiating an input mode of the second input/output unit for generating the third inversion for the second signal after the second inversion is detected by the first input/output unit in the first transmitting component in the second spare time; re-initiating an input mode of the third input/output unit for generating the fourth inversion for the first signal for transmitting the data bit representative completely after the third inversion is detected by the third input/output unit in the second transmitting component in the third spare time; and managing the transmission of another data bit representative to be initiated in one of the first transmitting component and the second transmitting component in the fourth spare time.

10. A method as claimed in claim 4 , further used for transmitting a batch of the data bit representatives, comprising a step of: (g) defining a first data bit representative of the batch as an initiating bit for initially transmitting the batch, wherein the initial bit is one of the high and low state data bit representatives.

11. A method as claimed in claim 4 , further used for transmitting a batch of a plurality of the data bit representatives, comprising a step of: (g) defining a desired number of the data bit representatives in the batch as an initiating segment, wherein the initiating segment constituted by a specific combination of a plurality of the relatively high state data bit representatives and a plurality of the relatively low state data bit representatives defines an initiation of the transmission of the batch.

12. A method as claimed in claim 4 , further used for transmitting a batch of the data bit representatives with a number of “n”, wherein the output component initially transmits the batch to the receiving component, comprising steps of: (q) substituting output/receive roles of the output component and the receiving component for each other when the output component transmits the batch completely; and (r) transmitting one of the relatively high state and the relatively low state data bit representatives as a responding bit for confirming a successful receipt of the batch.

13. A method as claimed in claim 12 , wherein the steps (q) and (r) are performed by steps of: repeatedly transmitting one of the relatively high state data bit representative and the relatively low state data bit representative n times; substituting the output component and the receiving component for each other; and transmitting one of the relatively high state and the relatively low state data bit representatives as the responding bit for confirming the successful receipt of the batch.

14. A method as claimed in claim 12 , wherein the steps (q) and (r) are performed by steps of: transmitting one of the relatively high state and the relatively low state data bit representative as an initiating bit for initially transmitting the batch; and repeatedly transmitting one of the relatively high state data bit representative and the relatively low state data bit representative n−1 times.

15. A method as claimed in claim 12 , wherein the steps (q) and (r) are performed by steps of: transmitting one of the relatively high state and the relative low state data bit representative as an initiating bit for initially transmitting the batch; repeatedly transmitting one of the relatively high state data bit representative and the relatively low state data bit representative n−1 times; substituting the output component and the receiving component for each other; and transmitting one of the relatively high state and relatively the low state data bit representatives as the responding bit for confirming the successful receipt of the batch.

16. A method as claimed in claim 14 , wherein the steps (q) and (r) are performed by steps of: transmitting one of the relatively high state and the relatively low state data bit representative as an initiating bit for initially transmitting the batch; repeatedly transmitting one of the relatively high state data bit representative and the relatively low state data bit representative n−2 times; and transmitting one of the relatively high state data bit representative and the relatively low state data bit representative as an end bit for ending transmitting the batch.

17. A method as claimed in claim 12 , wherein the steps (q) and (r) are performed by steps of: transmitting one of the relatively high state and the relatively low state data bit representative as an initiating bit for initially transmitting the batch; repeatedly transmitting one of the relatively high state data bit representative and the relatively low state data bit representative n−2 times; transmitting one of the relative high state data bit representative and the relative low state data bit representative as an end bit for ending transmitting the batch; substituting the output component and the receiving component for each other; and transmitting one of the relatively high state and the relatively low state data bit representatives as the responding bit for confirming the successful receipt of the batch.