Legal claims defining the scope of protection, as filed with the USPTO.
1. A device for testing a display port function, the device comprising: a display port transmitting part to transmit connecting signals to a display port timing controller mounted on a display panel; a field programmable gate array to apply a test signal to the display port timing controller and to control the connecting signals applied from the display port transmitting part to the display port timing controller; and a memory comprising a software that determines acceptance or rejection of the display port function based on data outputted from the display port timing controller, the data being output in response to the connecting signals or the test signal.
2. The device of claim 1 , further comprising a monitor to display a result of a determination of the display port function, is the determination being made by the software.
3. The device of claim 1 , wherein when a power on/off test is selected by the software, the field programmable gate array applies the test signal comprising a power on/off pulse to the display port timing controller to test normality of the power on/off of the display panel.
4. The device of claim 1 , wherein when a luminance up/down test is selected by the software, the field programmable gate array applies the test signal to the display port timing controller to test normality of the luminance up/down of the display panel, the test signal comprising a pulse having variable duties that may be stepwisely changed.
5. The device of claim 4 , wherein the software compares a duty of data output from the display port timing controller with a duty of reference data stored in the memory in response to the test signal comprising a pulse having a duty adjusted in stages, which is output from the field programmable gate array, to test normality of the luminance up/down of the display panel.
6. The device of claim 1 , wherein when an error mode transition test is selected by the software, the field programmable gate array applies the test signal comprising a frequency out of a normal range to the display port timing controller to test normality of the error mode transition of the display panel.
7. The device of claim 1 , wherein the connecting signals comprise: main link signals transmitted through a main channel to connect the display port timing controller with the display port transmitting part; and control signals transmitted through an auxiliary channel to control the display port timing controller.
8. The device of claim 7 , wherein when a low power mode transition test is selected by the software, the field programmable gate array blocks the main link signals to test normality of the low power mode transition of the display panel.
9. The device of claim 7 , wherein when a built-in self-test mode transition test is selected by the software, the field programmable gate array blocks the control signals to test normality of the built-in self test mode transition of the display panel.
10. The device of claim 1 , wherein when a safe mode transition test is selected by the software, the field programmable gate array applies the test signal of starting video distribution amplification to the display port timing controller to test normality of the safe mode transition of the display panel.
11. The device of claim 1 , wherein when a diagnostic mode transition test is selected by the software, the field programmable gate array applies the test signal comprising a diagnostic pulse to the display port timing controller to test normality of the diagnostic mode transition to the display panel.
12. A system for testing a display port function, the system comprising: a display panel comprising a display port timing controller; a device to test the display port function including: a display port transmitting part to transmit connecting signals to the display port timing controller; a field programmable gate array to apply a test signal to the display port timing controller and control the connecting signals applied from the display port transmitting part to the display port timing controller; and a memory comprising a software that determines acceptance or rejection of display port function based on data outputted from the display port timing controller, the data being output in response to the connecting signals or the test signal; and a display port cable connecting the display port timing controller to the device for testing the display port function.
13. The system of claim 12 , wherein the software tests at least one item selected from the group consisting of a power on/off test, a luminance up/down test, a safe mode transition test, a built-in self-test mode transition test, a diagnostic mode transition test, a low power mode transition test, and an error mode transition test.
14. A method of testing function of a display port, the method comprising: selecting a power on/off test; applying a first test signal comprising a power on/off pulse to a display port timing controller mounted on a display panel; outputting first data from the display port timing controller based on the first test signal; and determining normality of the power on/off of the display panel based on the first data.
15. The method of claim 14 , further comprising: selecting a luminance up/down test; applying a second test signal comprising a duty adjusted in stages to the display port timing controller; outputting second data from the display port timing controller based on the second test signal; and comparing the duty of the second data with a duty of reference data to test normality of the luminance up/down of the display panel.
16. The method of claim 14 , further comprising: selecting an error mode transition test; applying a second test signal comprising a frequency out of a normal range to the display port timing controller; outputting second data from the display port timing controller based on the second test signal; and determining normality of the error mode transition of the display panel based on the second data.
17. The method of claim 14 , further comprising: selecting a low power mode transition test; blocking application of the main link signals to the display port timing controller; outputting second data from the display port timing controller based on the blocking of the main link signals; and determining normality of the low power mode transition of the display panel based on the second data.
18. The method of claim 14 , further comprising: selecting a built-in self-test mode transition test; blocking application of control signals to the display port timing controller; outputting second data from the display port timing controller based on the blocking of the main link signals; and determining normality of the built-in self test mode transition of the display panel based on the second data.
19. The method of claim 14 , further comprising: selecting a safe mode transition test; applying a second test signal for starting video distribution amplification to the display port timing controller; outputting second data from the display port timing controller based on the second test signal; and determining normality of the safe mode transition of the display panel based on the second data.
20. The method of claim 14 , further comprising: selecting a diagnostic mode transition test; applying a second test signal comprising a diagnostic pulse to the display port timing controller; outputting second data from the display port timing controller based on the second test signal; and determining normality of the diagnostic mode transition of the display panel based on the second data.
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July 5, 2011
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