System and Method for Utilzing First-In-First-Out (fifo) Resources for Handling Differences in Data Rates Between Peripherals via a Merge Module That Merges Fifo Channels

1. A system for utilizing peripheral first-in-first-out (FIFO) resources, comprising: a processor; a first peripheral FIFO controller coupled to the processor and a first peripheral device for controlling a buffering of first data associated with the processor; a second peripheral FIFO controller coupled to the processor and a second peripheral device for controlling a buffering of second data associated with the processor; a merge module coupled to the first peripheral FIFO controller and the second peripheral FIFO controller; a first FIFO coupled to the merge module via a first FIFO channel; and a second FIFO coupled to the merge module via a second FIFO channel, wherein the merge module merges the first FIFO channel associated with the first peripheral FIFO controller and the second FIFO channel associated with the second peripheral FIFO controller based on an operational state of the first FIFO channel and an operational state of the second FIFO channel, and wherein the merge module merges the first FIFO channel and the second FIFO channel if only one of the first FIFO channel and the second FIFO channel is an active FIFO channel.

2. The system of claim 1 , wherein the operational state of the first FIFO channel is determined based on an operation type associated with the first FIFO channel and wherein the operational state of the second FIFO channel is determined based on an operation type associated with the second FIFO channel.

3. The system of claim 2 , further comprising a switch module for controlling the merge module based on the operational state of the first FIFO channel and the operational state of the second FIFO channel.

4. The system of claim 1 , wherein the merge module is operable to maintain the first FIFO channel and the second FIFO channel independent from each other if each of the first FIFO channel and the second FIFO channel is active.

5. The system of claim 1 , wherein the merge module is operable to add the second FIFO to the first FIFO channel if the first FIFO channel is active and the second FIFO channel is idle.

6. The system of claim 5 , wherein a write operation to the second FIFO is performed via the first FIFO channel if the first FIFO is full.

7. The system of claim 1 , wherein the merge module is operable to add the first FIFO to the second FIFO channel if the second FIFO channel is active and the first FIFO channel is idle.

8. The system of claim 7 , wherein a write operation to the first FIFO is performed via the second FIFO channel if the second FIFO is full.

9. The system of claim 1 , wherein the merge module comprises a plurality of multiplexers and de-multiplexers.

10. The system of claim 1 , wherein the first FIFO channel and the second FIFO channel are of a same type.

11. The system of claim 1 , wherein the first FIFO channel and the second FIFO channel are of different types.

12. A system on chip device (SOC), comprising: a processor; a plurality of peripheral FIFO controllers coupled to the processor and a respective one of a plurality of peripheral devices for controlling bufferings of data associated with the processor; a merge module coupled to the plurality of FIFO controllers; and a plurality of FIFOs coupled to the merge module via a plurality of FIFO channels, wherein the merge module merges the plurality of FIFO channels associated with the plurality of peripheral FIFO controllers based on operational states of the plurality of FIFO channels, wherein the plurality of FIFO channels includes a first FIFO channel and a second FIFO channel, and wherein the merge module merges the first FIFO channel and the second FIFO channel if only one of the first FIFO channel and the second FIFO channel is an active FIFO channel.

13. The device of claim 12 , wherein the operational states of the plurality of FIFO channels are determined based on a type of operation associated with each one of the plurality of FIFO channels.

14. The device of claim 12 , further comprising a switch module for controlling the merge module based on the operational states of the plurality of FIFO channels.

15. The device of claim 12 , wherein the merge module comprises a plurality of multiplexers and de-multiplexers.

16. A method for utilizing peripheral FIFO resources associated with a FIFO system with two FIFO channels, the method comprising: monitoring an operational state of a first FIFO channel associated with a first peripheral FIFO controller and an operational state of a second FIFO channel associated with a second peripheral FIFO controller, wherein the first peripheral FIFO controller is coupled to a first peripheral device and the second peripheral FIFO controller is coupled to a second peripheral device; merging the first FIFO channel coupled to a first FIFO and the second FIFO channel coupled to a second FIFO if only one of the first FIFO channel and the second FIFO channel is an active FIFO channel; and performing a FIFO operation using the active FIFO channel.

17. The method of claim 16 , wherein the monitoring the operational state of the first FIFO channel and the operational state of the second FIFO channel is based on at least one of: a write enable signal; a read enable signal; a FIFO empty signal; and a FIFO full signal.

18. The method of claim 16 , wherein the merging the first FIFO channel and the second FIFO channel comprises utilizing both the first FIFO and the second FIFO for the FIFO operation via the active FIFO channel.