Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory component comprising: a first pipeline path for selecting a least recently used (LRU) victim member from among a congruence class; and logic associated with the first pipeline path for responding to a selection of a bad victim by automatically initiating a selection, via LRU victim selection logic, of a next victim member from the congruence class in place of the bad victim, wherein said LRU victim selection logic further comprises: logic for randomly picking a member of the congruence class to assign as the LRU victim member; and logic for deterministically selecting the LRU victim member from among a randomly selected member and the member that is indicated by LRU state bits, wherein the randomly selected member is selected as the LRU victim member in response to the member indicated by the LRU state bits exhibiting a pre-identified condition that identifies the member as a bad victim.
2. The memory component of claim 1 , said first pipeline path comprising: an LRU state array with a plurality of LRU state bits indicating a least recently used member of the congruence class; and wherein the LRU victim selection logic receives said LRU state bits as a first input and issues an output vector identifying the selected LRU victim member.
3. The memory component of claim 2 , further comprising: LRU mode logic that responds to a selection of a bad victim by issuing an LRU mode select input that triggers said LRU victim selection logic to pick the randomly selected member as the victim member, wherein the LRU mode select input defaults to allow a selection of the victim member indicated by the LRU state bits when there is no selection of a bad victim.
4. The memory component of claim 2 , further comprising: logic for restarting the LRU victim selection logic to select the next victim member when the previous selection resulted in selection of a bad victim.
5. The memory component of claim 2 , further comprising: logic for discarding a victim vector outputted from the LRU victim selection logic when the victim vector points to a bad victim.
6. The memory component of claim 2 , further comprising: an error checking logic that determines when the selected victim member is a bad victim, said bad victim being one of a faulty member within a cache line that does not provide proper caching operation, a deleted member, and a phantom member indicated by the LRU state bits when the LRU state bits do not point to one of the members of the congruence class.
7. The memory component of claim 6 , wherein said error checking logic comprises: comparison logic for determining when a victim vector outputted from the LRU victim selection logic does not point to any of the members in the congruence class; comparison logic for determining when the victim vector is a faulty member, such as a deleted member; and output response mechanism for triggering a restart of the victim selection process at the LRU victim selection logic when either comparison yields a positive results.
8. A computer system comprising: a processor; and a memory component comprising: a first pipeline path for selecting a least recently used (LRU) victim member from among a congruence class; and a mechanism associated with the first pipeline path for responding to a selection of a bad victim member by initiating an automatic selection of a next victim member from the congruence class in place of the bad victim, said mechanism further including LRU mode logic that responds to a selection of the bad victim by issuing an LRU mode select input that triggers LRU victim selection logic to pick a randomly selected member as the victim member of the congruence class, wherein the LRU mode select input defaults to allow a selection of the victim member indicated by the LRU state bits when the victim member is not a bad victim.
9. The computer system of claim 8 , said first pipeline path comprising: an LRU state array with a plurality of LRU state bits indicating a least recently used member of the congruence class; and an LRU victim selection logic that receives said LRU state bits as a first input and which issues an output vector identifying the selected LRU victim member.
10. The computer system of claim 9 , wherein said LRU victim selection logic further comprises: logic for randomly picking a member to assign as the LRU victim member; and logic for deterministically selecting the LRU victim member from among the randomly selected member and a member that is indicated by the LRU state bits.
11. The computer system of claim 9 , said mechanism further comprising: logic for restarting the LRU victim selection logic to select the next victim member when the previous selection resulted in selection of a bad victim.
12. The computer system of claim 9 , said mechanism further comprising: logic for discarding a victim vector outputted from the LRU victim selection logic when the victim vector points to a bad victim.
13. The computer system of claim 9 , said mechanism further comprising: an error checking logic that determines when the selected victim member is a bad victim, said bad victim being one of a faulty member within a cache line that does not provide proper caching operation, a deleted member, and a phantom member indicated by the LRU state bits when the LRU state bits do not point to one of the members of the congruence class.
14. The computer system of claim 13 , wherein said error checking logic comprises: comparison logic for determining when a victim vector outputted from the LRU victim selection logic does not point to any of the members in the congruence class; comparison logic for determining when the victim vector is a faulty member, such as a deleted member; and output response mechanism for triggering a restart of the victim selection process at the LRU victim selection logic when either comparison yields a positive results.
Unknown
July 26, 2011
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