Block Redundancy Implementation in Hierarchical Rams

1. A hierarchal memory structure, comprising: a plurality of predecoders that select blocks of memory cells; a redundant predecoder that selects a redundant block of memory cells; and a redundancy control circuit that generates a redundancy select signal based on a programmed block address information, wherein a shift pointer is controlled by redundancy logic circuitry that processes an address range that is responsible for tagging each block of memory cells.

2. The hierarchal memory structure of claim 1 , wherein the redundancy control circuit is responsible for shifting out one of the plurality of predecoders and shifting in the redundant predecoder.

3. The hierarchal memory structure of claim 1 , wherein any one of the blocks of memory cells is identical in size to the redundant block of memory cells.

4. The hierarchal memory structure of claim 1 , wherein each of the plurality of predecoders provide a localized enable signal for a set of decoders that decode an address space within one of the block of memory cells.

5. The hierarchal memory structure of claim 1 , wherein the redundant predecoder acts provides a localized enable signal for a set of redundant decoders that decode an address space within the redundant block of memory cells.

6. The hierarchal memory structure of claim 1 , wherein the address range received by the redundant predecoder that accesses the memory cells in the redundant block is the same as the address range received by at least one of the plurality of predecoders accessing the memory cells in one of the blocks.

7. A method for replacing a predecoder, said method comprising: selecting blocks of memory cells with a plurality of predecoders; generating a redundancy select signal based on a programmed block address information; shifting out one of the plurality of predecoders and shifting in a redundant predecoder, wherein a shift pointer is controlled by redundancy logic circuitry that processes an address range that is responsible for tagging each block of memory cells; and selecting a redundant block of memory cells with the redundant predecoder.

8. The method of claim 7 , wherein any one of the blocks of memory cells is identical in size to the redundant block of memory cells.

9. The method of claim 7 , further comprising: providing a localized enable signal for a set of decoders that decode an address space within one of the block of memory cells.

10. The method of claim 7 , further comprising: provides a localized enable signal for a set of redundant decoders that decode an address space within the redundant block of memory cells from the redundant predecoder.

11. The method of claim 7 , wherein the address range received by the redundant predecoder that accesses the memory cells in the redundant block is the same as the address range received by at least one of the plurality of predecoders accessing the memory cells in one of the blocks.

12. The hierarchal memory structure of claim 1 , wherein the plurality of predecoders includes an active predecoder that is configured to be shifted out of use, and wherein the redundant predecoder is configured to be shifted in to use.

13. The hierarchal memory structure of claim 1 , wherein the hierarchical memory structure is embedded within one or more of the following: a VLSI system, a VLSI memory subsystem, and a digital signal processing system.

14. The hierarchal memory structure of claim 1 , wherein the hierarchical memory structure is part of SRAM.

15. The hierarchal memory structure of claim 1 , wherein the hierarchical memory structure is part of an SRAM memory structure.

16. The hierarchal memory structure of claim 1 , wherein the memory cells comprise one or more of the following: CMOS memory cells and CMOS SRAM memory cells.

17. The hierarchal memory structure of claim 1 , wherein the hierarchical memory structure is part of one or more of the following: DRAM, RAM, ROM, PLA, and a stand-alone memory device.

18. The hierarchical memory structure of claim 1 , wherein the hierarchical memory structure employs switched capacitance reduction and voltage swing limitation techniques to reduce power consumption.

19. The hierarchical memory structure of claim 1 , wherein the hierarchical memory structure is part of one or more of the following: a communications system and a DSP device.

20. The hierarchical memory structure of claim 1 , wherein the hierarchical memory structure employs a synchronous, self-timed hierarchical architecture.