Digital Signal Processor Having a Plurality of Independent Dedicated Processors

1. A digital signal processor comprising: a mathematical processor; an input processor to process input signals received from a first buffer coupled to the input processor; an output processor to process output signals to be output via a second buffer coupled to the output processor; a master processor to control the mathematical processor, the input processor and the output processor, and to provide synchronization for the other processors; and a storage to store data from each of the processors so as to be accessible by each of the processors, the storage including a plurality of registers, including a first register to transfer data from the first register to a second register when new data is written into the first register.

2. The digital signal processor of claim 1 , further including a random access memory processor to store intermediate calculation results.

3. The digital signal processor of claim 2 , including a bus to couple each of the processors to the storage.

4. The digital signal processor of claim 1 , wherein the input and output processors are to implement mathematical operations.

5. The digital signal processor of claim 1 , wherein the processors are to communicate with one another through the storage.

6. The digital signal processor of claim 1 , wherein each of the processors includes its own random access memory.

7. The digital signal processor of claim 1 , wherein the mathematical processor is to cause the data to be transferred from one register to another.

8. The digital signal processor of claim 1 , wherein each of the processors has a different instruction set than the other processors.

9. The digital signal processor of claim 1 , wherein the first register is to transfer the data and write the new data in a single clock signal, and the second register is to transfer a second existing data to a third register in the single clock cycle.

10. The digital signal processor of claim 1 , wherein the transfer of the data is performed without execution of a register to register move instruction.

11. A method comprising: using a first processor to process input signals received from a first buffer coupled to the first processor; using a second processor to process output signals to be output via a second buffer coupled to the second processor; using a third processor for multiply and accumulate operations; controlling the first, second and third processors using a fourth processor; and storing data from one of the processors in a first register, transferring a prior value stored in the first register into a second register, and transferring a second prior value stored in the second register into a third register, when an end of chain value is greater than a start of chain value.

12. The method of claim 11 , including automatically transferring the prior value from the first register to the second register when the data is being written into the first register.

13. The method of claim 12 , including automatically transferring the prior value in response to action by the first processor.

14. The method of claim 12 , including storing a bit to indicate which processor may control the automatic transfer of data from one register to another.

15. The method of claim 11 , including providing each of the processors with a different instruction set than the other processors.

16. The method of claim 11 , including transferring the prior value without execution of a register to register move instruction.

17. An apparatus comprising: a plurality of mathematical processors to perform arithmetic operations on data; a master processor to control the plurality of mathematical processors; and a storage to store data from each of the plurality of mathematical processors so as to be accessible by each of the mathematical processors, the storage including a plurality of registers, including a first register to transfer data from the first register to a second register when new data is written into the first register.

18. The apparatus of claim 17 , further comprising an input processor to process input signals received from a first buffer coupled to the input processor.

19. The apparatus of claim 18 , further comprising an output processor to process output signals to be output via a second buffer coupled to the output processor.