Legal claims defining the scope of protection, as filed with the USPTO.
1. A powered device (PD), comprising: an input port that receives a port voltage; a first circuit, coupled to the input port, configured to couple the port voltage to a detection resistor when the port voltage is within a detection voltage range; a second circuit, coupled to the input port, configured to couple the port voltage to a classification resistor when the port voltage is within a classification voltage range; a third circuit, coupled to the input port, configured to couple the port voltage to a PD load when the port voltage is within a start up voltage range; and a fourth circuit, coupled to the input port, configured to clamp down the port voltage to within a supported port voltage range of the PD when the port voltage exceeds a maximum of the supported port voltage range.
2. The PD of claim 1 , wherein one or more of the first, second, third, and fourth circuit is integrated within a PD chip of the PD.
3. The PD of claim 2 , wherein one or more of the detection resistor and the classification resistor is integrated within the PD chip.
4. The PD of claim 2 , wherein one or more of the detection resistor and the classification resistor is external to the PD chip.
5. The PD of claim 1 , wherein the start up voltage range includes a minimum of 36 volts and a maximum of 57 volts.
6. The PD of claim 2 , wherein the third circuit couples the port voltage to the PD load via a Hot Swap MOSFET when the port voltage is within the start up voltage range.
7. The PD of claim 6 , wherein the Hot Swap MOSFET is integrated within the PD chip or external to the PD chip.
8. The PD of claim 1 , wherein the supported port voltage range is that supported by a process of an IEEE compliant PD.
9. The PD of claim 1 , wherein the maximum of the supported port voltage range is 57 volts.
10. The PD of claim 1 , wherein the maximum of the supported port voltage range is equal to a maximum of the start up voltage range.
11. The PD of claim 1 , wherein the fourth circuit is triggered to clamp down the port voltage when a PD in-rush current during a start up phase of the PD is lower than a predetermined value.
12. The PD of claim 1 , wherein the fourth circuit is triggered to clamp down the port voltage when a current drawn by the PD load is lower than a maximum post start up load current.
13. The PD of claim 12 , wherein the maximum post start up load current is specified by IEEE 802.3af.
14. The PD of claim 1 , wherein the input port receives the port voltage over a cable from a power source equipment (PSE).
15. The PD of claim 14 , wherein the fourth circuit is triggered to clamp down the port voltage when a voltage drop across the cable is lower than a difference between a voltage provided by the PSE and the maximum of the supported port voltage range of the PD.
16. The PD of claim 15 , wherein the fourth circuit is triggered when a current drawn by the PD load is not sufficiently high to cause the voltage drop across the cable to be greater than said difference.
17. The PD of claim 14 , wherein the fourth circuit is implemented within a dongle coupled between the cable and the input port of the PD.
18. The PD of claim 1 , wherein the fourth circuit couples the port voltage to a dummy load when the port voltage exceeds the maximum of the supported port voltage range of the PD.
19. The PD of claim 18 , wherein a value of the dummy load is selected according to a class of the PD.
20. The PD of claim 1 , further comprising: a pulse width modulation (PWM) controller.
Unknown
October 4, 2011
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