Memory Organizational Scheme and Controller Architecture for Image and Video Processing

1. A method comprising: accessing a first memory word of a memory that includes first pixel data for a first location in a first image and first pixel data for a first location in a second image, the first location of the first image and the second image being the same, wherein the first and second images are different images; accessing a second memory word of the memory that includes second single pixel data for a second location in the first image and second pixel data for a second location in the second image, the second location of the first image and the second image being the same; and delivering the first pixel data of the first image to a first image processing module and delivering the first pixel data of the second image to a second image processing module.

2. The method of claim 1 , further comprising accessing a third memory word of the memory that includes third single pixel data of a first image and third single pixel data of the second image.

3. The method of claim 1 , wherein the first memory word further includes first pixel data of a third image and wherein the second memory word further includes second pixel data of the third image.

4. The method of claim 1 , wherein the first and second memory words comprise contiguous rows of the memory.

5. The method of claim 1 , wherein contiguous pixels of the first and second images are stored in contiguous rows of the memory and the first and second memory words each include pixels from a plurality of images.

6. The method of claim 1 , further comprising: accessing the first memory word from the memory in a memory access cycle to concurrently retrieve the first pixel data and the second pixel data; delivering the first pixel data of the first image to the first image processing module in response to accessing the first memory word in the memory access cycle; and delivering the first pixel data of the second image to the second image processing module in response to accessing the first memory word in the memory access cycle.

7. The method of claim 6 , further comprising: processing the first pixel data of the first image in the first image processing module; and simultaneously processing the first pixel data of the second image in the second image processing module.

8. The method of claim 7 , further comprising: combining a processed version of the first pixel data of the first image with a processed version of the first pixel data of the second image in a common memory word; and storing the common memory word back to the memory in the different memory access cycle.

9. The method of claim 1 , further comprising: accessing the first memory word from the memory in a memory access cycle; delivering the first pixel data of the first and second images to the first and second image processing modules in response to accessing the first memory word in the memory access cycle; processing the first pixel data of the first and second images in the image processing modules; and storing a processed version of the first pixel data of the first and second images back to the memory in a different memory access cycle wherein the processed versions of the first pixel data of the first and second images are stored in a common memory word of the memory.

10. The method of claim 1 , further comprising accessing non-pixel data in the memory.

11. The method of claim 1 , wherein the first memory word conforms to a width of an instruction executable by a processor, the method further comprising storing first pixel data from a plurality of images including the first image and the second image to pack an entire width of the first memory word with pixel data.

12. A device comprising: a memory configured to store a first memory word that includes first pixel data for a first location in a first image and first pixel data for a first location in a second image, the first location of the first image and the second image being the same, and a second memory word that includes second single pixel data for a second location in the first image and second pixel data for a second location in the second image, the second location of the first image and the second image being the same, wherein the first and second images are different images; and a controller that accesses the first memory word in a memory access cycle to deliver the first pixel data of the first image to a first image processing module and to deliver the first pixel data of the second image to a second image processing module.

13. The device of claim 12 , wherein the memory is configured to store a third memory word that includes third single pixel data of a first image and third single pixel data of the second image.

14. The device of claim 12 , wherein the first memory word further includes first pixel data of a third image and wherein the second memory word further includes second pixel data of the third image.

15. The device of claim 12 , wherein the first and second memory words comprise contiguous rows of the memory.

16. The device of claim 12 , wherein contiguous pixels of the first and second images are stored in contiguous rows of the memory and the first and second memory words each include pixels from a plurality of images of a video sequence.

17. The device of claim 12 , further comprising: the first image processing module; and the second image processing module, wherein the controller delivers the first pixel data of the first image to the first image processing module in response to accessing the first memory word in the memory access cycle, and the controller delivers the first pixel data of the second image to the second image processing module in response to accessing the first memory word in the memory access cycle.

18. The device of claim 17 , further wherein: the first image processing module processes the first pixel data of the first image; and the second image processing module simultaneously processes the first pixel data of the second image.

19. The device of claim 18 , further wherein: the controller combines a processed version of the first pixel data of the first image with a processed version of the first pixel data of the second image in a common memory word; and the controller stores the common memory word back to the memory in the different memory access cycle.

20. The device of claim 12 , further comprising the first and second image processing modules, wherein: the controller delivers the first pixel data of the first and second images to the image processing modules in response to accessing the first memory word in the memory access cycle; the image processing modules process the first pixel data of the first and second images; and the controller stores a processed version of the first pixel data of the first and second images back to the memory in a different memory access cycle, wherein the processed versions of the first pixel data of the first and second images are stored in a common memory word of the memory.

21. The device of claim 12 , wherein the memory is further configured to store non-pixel data.

22. The device of claim 12 , further comprising: a processor capable of executing instructions; wherein the first memory word conforms to a width associated with the instructions, and wherein the memory stores first pixel data from a plurality of images including the first image and the second image to pack an entire width of the first memory word with pixel data from the plurality of images.

23. A memory controller, wherein the memory controller is configured to: access a first memory word stored in a memory that includes first pixel data for a first location in a first image and first pixel data for a first location in a second image, the first location of the first image and the second image being the same, wherein the first and second images are different images; access a second memory word stored in the memory that includes second single pixel data for a second location in the second image, the second location of the first image and the second image being the same; deliver the first pixel data of the first image to a first image processing module; and deliver the first pixel data of the second image to a second image processing module.

24. The memory controller of claim 23 , further being configured to access a third memory word that includes third single pixel data of a first image and third single pixel data of the second image.

25. The memory controller of claim 23 , wherein the first memory word further includes first pixel data of a third image and wherein the second memory word further includes second pixel data of the third image.

26. The memory controller of claim 23 , wherein the first and second memory words comprise contiguous rows of the memory.

27. The memory controller of claim 23 , wherein contiguous pixels of the first and second images are stored in contiguous rows of the memory and the first and second memory words each include pixels from a plurality of images of a video sequence.

28. The memory controller of claim 23 , further being configured to access non-pixel data stored in the memory.

29. The memory controller of claim 23 , wherein the memory words comprise 64 bits and the first and second pixels each comprise 8 bits.

30. The memory controller of claim 29 , further wherein: the first memory word includes first pixel data of a third image and the second memory word includes second pixel data of the third image; the first memory word includes first pixel data of a fourth image and the second memory word includes second pixel data of the fourth image; the first memory word includes first pixel data of a fifth image and the second memory word includes second pixel data of the fifth image; the first memory word includes first pixel data of a sixth image and the second memory word includes second pixel data of the sixth image; the first memory word includes first pixel data of a seventh image and the second memory word includes second pixel data of the seventh image; and the first memory word includes first pixel data of an eighth image and the second memory word includes second pixel data of the eighth image.

31. The memory controller of claim 29 , wherein the memory includes at least 512 rows that define at least 512 memory words, each of which includes pixel data of two or more images.

32. The method of claim 1 , further comprising encoding the first image and the second image.

33. The device of claim 12 , further comprising a coding unit configured to encode the first image and the second image.

34. The memory controller of claim 23 , further being configured to encode the first image and the second image.

35. The method of claim 1 , further comprising performing at least one of demosaicing, lens rolloff correction, scaling, color correction, color conversion, and spatial filtering on the first pixel data of the first image and the first pixel data of the second image in parallel.

36. The device of claim 12 , wherein the first image processing module and the second image processing module are configured to perform at least one of demosaicing, lens rolloff correction, scaling, color correction, color conversion, and spatial filtering on the first pixel data of the first image and the first pixel data of the second image respectively in parallel.

37. The memory controller of claim 23 , further being configured to perform at least one of demosaicing, lens rolloff correction, scaling, color correction, color conversion, and spatial filtering on the first pixel data of the first image and the first pixel data of the second image in parallel.