Performance Monitor Unit for Sampling All Performance Events Generated by a Processor

1. A performance monitor hardware unit that is included in a processor, the performance monitor hardware unit monitoring the performance of the processor, the performance monitor hardware unit comprising: a plurality of hardware counters that count only a selected subset of a plurality of performance event signals received by the performance monitor hardware unit; a hardware event register that intercepts the plurality of performance event signals and outputs the selected subset of the plurality of performance signals to the plurality of hardware counters; a single unit in the hardware event register that stores current values of the plurality of performance event signals received by the processor, the single unit being a full set of available performance event signals that indicates the current full event state of the processor at a particular time; control logic that is coupled to the hardware event register utilizing a freeze state line; control logic that receives a notification of a freeze condition; control logic that causes the hardware event register to enter a freeze state in response to the control logic receiving the notification of the freeze condition; control logic that receives the notification that the freeze condition no longer exists; and control logic that causes the hardware event register to enter a normal, non-freeze state in response to the control logic receiving the notification that the freeze condition no longer exists.

2. The performance monitor hardware unit according to claim 1 , further comprising: the control logic copying the single unit currently stored in the hardware event register to memory in response to the control logic receiving the notification of a freeze condition.

3. The performance monitor hardware unit according to claim 1 , wherein the hardware event register causes the single unit stored in the hardware event register to be copied to memory in response to the hardware event register entering the freeze state.

4. The performance monitor hardware unit according to claim 1 , wherein the hardware event register is software accessible; and the single unit stored in the hardware event register is accessed by a software routine that copies the single unit from the hardware event register to memory.

5. The performance monitor hardware unit according to claim 1 , wherein the hardware event register receives a new set of performance event signals and overwrites the current values of the plurality of performance event signals upon each occurrence of a clock cycle.

6. The performance monitor hardware unit according to claim 1 , wherein the performance monitor hardware unit includes at least one multiplexer that receives at least two of the plurality of performance event signals, and wherein an output of the multiplexer is connected to the hardware event register.

7. The performance monitor hardware unit according to claim 1 , further comprising a dedicated physical wire that is connected to a monitored unit and to the hardware event register, wherein the performance monitor hardware unit receives a particular one of the plurality of performance signals using the dedicated physical wire.

8. The performance monitor hardware unit according to claim 1 , wherein the performance monitor hardware unit includes at least one multiplexer that receives at least two of the plurality of performance event signals, and wherein an output of the multiplexer is connected to the hardware event register; and further comprising a dedicated physical wire that is connected to a monitored unit and to the hardware event register, wherein the performance monitor hardware unit receives a particular one of the plurality of performance signals using the dedicated physical wire.

9. The performance monitor hardware unit according to claim 1 , further comprising a completion unit that generates one of the plurality of performance signals.

10. A computer program product, comprising a non-transitory computer recordable medium in a performance monitor hardware unit, the computer recordable medium tangibly embodying a plurality of instructions executable by a processor, the instructions comprising: instructions for receiving, within the performance monitor hardware unit, a plurality of performance event signals, a plurality of performance event signals indicating a current full event state of the processor at a particular time; instructions for counting only a selected subset of the plurality of performance event signals by a plurality of hardware counters included in the performance monitor hardware unit; instructions for intercepting, by a hardware event register included in the performance monitor hardware unit, the plurality of performance event signals; and instructions for outputting, by the hardware event register, the selected subset of the performance signals to the plurality of counters; instructions for storing current values of the plurality of performance event signals together as a single unit in the hardware event register, the single unit being a full set of available performance event signals that indicate the current full event state of the processor at a particular time; instructions for storing current values of the plurality of performance event signals together as a single unit in the hardware event register upon each occurrence of a clock cycle; and instructions for overwriting the current values of the hardware event register upon each clock cycle.

11. The computer program product according to claim 10 , further comprising control logic that is included in the performance monitor being coupled to the hardware event register utilizing a freeze state line, the computer recordable medium further comprising: instructions for receiving, by the control logic, a notification of a freeze condition; instructions for causing, by the control logic, the hardware event register to enter a freeze state in response to the control logic receiving the notification of the freeze condition; instructions for receiving, by the control logic, a notification that the freeze condition no longer exists; and instructions for causing, by the control logic, the hardware event register to enter a normal, non-freeze state in response to the control logic receiving the notification that the freeze condition no longer exists.

12. The computer program product according to claim 11 , further comprising: instructions for copying, by the control logic, the single unit currently stored in the hardware event register to memory in response to the control logic receiving the notification of a freeze condition.

13. The computer program product according to claim 11 , further comprising: instructions for causing, by the hardware event register, the single unit stored in the hardware event register to be copied to memory in response to the hardware event register entering the freeze state.

14. The computer program product according to claim 10 , further comprising: instructions for copying the single unit stored in the hardware event register from the hardware event register.

15. The computer program product according to claim 10 , wherein the performance monitor hardware unit includes at least one multiplexer that receives at least two of the plurality of performance event signals, and wherein an output of the multiplexer is connected to the hardware event register.

16. The computer program product according to claim 10 , further comprising a dedicated physical wire that is connected to a monitored unit and to the hardware event register, wherein the performance monitor hardware unit receives a particular one of the plurality of performance signals using the dedicated physical wire.

17. The computer program product according to claim 10 , wherein the performance monitor hardware unit includes at least one multiplexer that receives at least two of the plurality of performance event signals, and wherein an output of the multiplexer is connected to the hardware event register; and further comprising a dedicated physical wire that is connected to a monitored unit and to the hardware event register, wherein the performance monitor hardware unit receives a particular one of the plurality of performance signals using the dedicated physical wire.

18. A performance monitor hardware unit that is included in a processor, the performance monitor hardware unit monitoring the performance of the processor, the performance monitor hardware unit comprising: a plurality of hardware counters that count only a selected subset of a plurality of performance event signals received by the performance monitor hardware unit; a hardware event register that intercepts the plurality of performance event signals and outputs the selected subset of the plurality of performance signals to the plurality of hardware counters; at least one multiplexer that receives at least two of the plurality of performance event signals, and wherein an output of the multiplexer is connected to the hardware event register; wherein the hardware event register receives a new set of performance event signals and overwrites the current values of the plurality of performance event signals upon each occurrence of a clock cycle; and a single unit in the hardware event register that stores current values of the plurality of performance event signals received by the processor, the single unit being a full set of available performance event signals that indicates the current full event state of the processor at a particular time.

19. A performance monitor hardware unit comprising: means for receiving, within the performance monitor hardware unit, a plurality of performance event signals, wherein the plurality of performance event signals indicate a current full event state of the processor at a particular time; means for counting only a selected subset of the plurality of performance event signals by a plurality of hardware counters included in the performance monitor hardware unit; means for intercepting, by a hardware event register included in the performance monitor hardware unit, the plurality of performance event signals; means for outputting, by the hardware event register, the selected subset of the performance signals to the plurality of counters; means for storing current values of the plurality of performance event signals together as a single unit in the hardware event register, wherein the single unit is a full set of available performance event signals that indicate the current full event state of the processor at a particular time; means for storing current values of the plurality of performance event signals together as a single unit in the hardware event register upon each occurrence of a clock cycle; and means for overwriting the current values of the hardware event register upon each clock cycle.