Data Writing Method for Non-Volatile Memory and Controller Using the Same

1. A data writing method for a non-volatile memory, wherein the non-volatile memory is a MLC NAND flash memory, and each block in the non-volatile memory comprises upper pages and lower pages, the data writing method comprising: using only the lower pages for writing data in a part of the blocks, wherein the write speed of the lower pages is faster than the write speed of the upper pages, wherein the part of the blocks is a plurality of temporary blocks, and the temporary blocks are used as a temporary area of a plurality of blocks in a substitution area.

2. The data writing method according to claim 1 further comprising using only the lower pages of each block for writing the data.

3. The data writing method according to claim 1 , wherein the data comprises at least one of a logical-physical mapping table, a cache file, a file allocation table (FAT), a firmware code, a defect block table (DBT) for recording defective blocks, a replace unit table (RUT) for managing defective block replacement, an info block for storing firmware parameters, and a variable table (VT) for storing variables.

4. The data writing method according to claim 1 further comprising establishing a page query table for recording the physical addresses of the lower pages.

5. The data writing method according to claim 1 further comprising establishing a logic conversion formula for calculating the physical addresses of the lower pages.

6. A controller, suitable for a storage device, wherein a non-volatile memory of the storage device is a MLC NAND flash memory, and each block in the non-volatile memory comprises upper pages and lower pages, the controller comprising: a microprocessor unit, for controlling the operation of the controller; a non-volatile memory interface, electrically connected to the microprocessor unit and used for accessing the non-volatile memory; a buffer memory, electrically connected to the microprocessor unit and used for temporarily storing data; and a memory management module, electrically connected to the microprocessor unit and used for managing the non-volatile memory, wherein the memory management module only uses the lower pages for writing data in a part of the blocks, wherein the write speed of the lower pages is faster than the write speed of the upper pages, wherein the part of the blocks is a plurality of temporary blocks, and the temporary blocks are used as a temporary area of a plurality of blocks in a substitution area.

7. The controller according to claim 6 , wherein the memory management module uses only the lower pages in each block for writing the data.

8. The controller according to claim 6 , wherein the data comprises at least one of a logical-physical mapping table, a cache file, a FAT, a firmware code, a DBT for recording defective blocks, a RUT for managing defective block replacement, an info block for storing firmware parameters, and a VT for storing variables.

9. The controller according to claim 6 , wherein the memory management module establishes a page query table for recording the physical addresses of the lower pages.

10. The controller according to claim 6 , wherein the memory management module establishes a logic conversion formula for calculating the physical addresses of the lower pages.