Automated Processor Generation System and Method for Designing a Configurable Processor

1. A computer-implemented system for designing a configurable processor, the system comprising: hardware generation means for, based on a user-defined specification, generating a description of a hardware implementation of the processor; and software generation means for, based on the user-defined specification, generating software development tools specific to the hardware implementation; wherein the user-defined specification includes a user-defined specification of a processor exception and when a processor instruction raises the exception; and the hardware generation means includes user-defined exception support generating means for generating hardware supporting the user-defined specification of the processor exception as part of the processor hardware implementation.

2. A computer-implemented system according to claim 1 , wherein the user-defined specification of the processor exception includes priority information associated with the processor exception.

3. A computer-implemented system according to claim 2 , wherein the user-defined exception support generating means includes means for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals in accordance with the priority information.

4. A computer-implemented system according to claim 1 , wherein the user-defined exception support generating means includes means for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals.

5. A computer-implemented system according to claim 1 , wherein the user-defined exception support generating means includes means for encoding a signal from the hardware supporting the user-defined specification of the processor exception with a priority level.

6. A computer-implemented system according to claim 1 , wherein the user-defined exception support generating means includes means for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals.

7. A computer-implemented system according to claim 1 , wherein the user-defined specification of the processor exception includes a schedule declaration associated with when the processor instruction raises the exception.

8. A computer-implemented system according to claim 7 , wherein the schedule declaration includes a pipeline stage associated with execution of the instruction.

9. A computer-implemented method for designing a configurable processor, the system comprising: based on a user-defined specification, generating a description of a hardware implementation of the processor; and based on the user-defined specification, generating software development tools specific to the hardware implementation; wherein the user-defined specification includes a user-defined specification of a processor exception and when a processor instruction raises the exception; and the hardware generation step includes generating hardware supporting the user-defined specification of the processor exception as part of the processor hardware implementation.

10. A computer-implemented method to claim 9 , wherein the user-defined specification of the processor exception includes priority information associated with the processor exception.

11. A computer-implemented method according to claim 10 , wherein the hardware generating step includes generating hardware for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals in accordance with the priority information.

12. A computer-implemented method according to claim 9 , wherein the hardware generating step includes generating hardware for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals.

13. A computer-implemented method according to claim 9 , wherein the hardware generating step includes generating hardware for encoding a signal from the hardware supporting the user-defined specification of the processor exception with a priority level.

14. A computer-implemented method according to claim 9 , wherein the hardware generating step includes generating hardware for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals.

15. A computer-implemented method according to claim 9 , wherein the user-defined specification of the processor exception includes a schedule declaration associated with when the processor instruction raises the exception.

16. A computer-implemented method according to claim 15 , wherein the schedule declaration includes a pipeline stage associated with execution of the instruction.