Method for Debugger Initiated Coherency Transactions Using a Shared Coherency Manager

1. A data processing system comprising: a system interconnect; a first interconnect master coupled to the system interconnect, the first interconnect master having a cache; a second interconnect master coupled to the system interconnect; and a cache coherency manager coupled to the first and second interconnect masters and an external debugger, wherein the cache coherency manager provides debug cache coherency operations and non-debug cache coherency operations to the first interconnect master, the cache coherency manager generates the debug cache coherency operations in response to debug cache coherency commands from the external debugger and generates the non-debug cache coherency operations in response to transactions performed by the second interconnect master on the system interconnect, the cache coherency manager provides second debug cache coherency operations and second non-debug cache coherency operations to the second interconnect master, and the cache coherency manager generates the second debug cache coherency operations in response to second debug cache coherency commands from the external debugger and generates the non-debug cache coherency operations in response to transactions performed by the first interconnect master on the system interconnect.

2. The data processing system of claim 1 , wherein the debug cache coherency operations are generated in response to the debug cache coherency commands provided via a debug interface from the debugger.

3. The data processing system of claim 1 , wherein the debug cache coherency operations are generated in response to the debug cache coherency commands without placing a portion of the data processing system in a halted mode.

4. The data processing system of claim 1 , wherein the first interconnect master processes cache coherency operations from the cache coherency manager, the cache coherency operations including both non-debug cache coherency operations and debug cache coherency operations, wherein, in response to processing a cache coherency operation whose corresponding access address hit a cache line in the cache, provides a cache coherency response which includes a previous coherency state of the cache line.

5. The data processing system of claim 4 , wherein the previous coherency state of the cache line is provided according to a MESI protocol including an invalid state, an exclusive state, a shared state, and a modified state.

6. The data processing system of claim 4 , wherein, in response to processing the cache coherency operation whose corresponding access address hit the cache line in the cache, the previous coherency state of the cache line is selectively transitioned to a new coherency state.

7. The data processing system of claim 1 , wherein the second interconnect master comprises a cache, and wherein a first debug cache coherency command of the debug cache coherency commands can identify one or more caches of the data processing system on which to perform a first debug cache coherency operation generated in response to the first debug cache coherency command.

8. The data processing system of claim 1 , wherein a first debug cache coherency command of the debug cache coherency commands provides priority information, wherein the cache coherency manager defines a priority for a first debug cache coherency operation generated in response to the first debug cache coherency command based on the priority information.

9. The data processing system of claim 1 , further comprising: trigger control logic which provides a trigger signal to indicate when a debug cache coherency operation is to be provided from the cache coherency manager to the first interconnect master for processing.

10. In a data processing system having a first interconnect master, a second interconnect master, and a system interconnect coupled to the first interconnect master and the second interconnect master, a method comprising: buffering a debug cache coherency operation and at least one additional debug cache coherency operation; providing the debug cache coherency operation to the first interconnect master, wherein said providing the debug cache coherency operation is performed subsequent to said buffering the debug cache coherency operation and the at least one additional debug cache coherency operation, said providing the debug cache coherency operation is performed in response to a number of currently buffered debug cache coherency operations reaching a threshold value, and the debug cache coherency operation is generated in response to a debug cache coherency command from a debugger external to the data processing system; and providing a non-debug cache coherency operation to the first interconnect master, wherein the non-debug cache coherency operation is generated in response to a snooped transaction performed by the second interconnect master via a system interconnect.

11. The method of claim 10 , further comprising: processing, by the first interconnect master, the debug cache coherency operation and, in response thereto, providing a debug cache coherency response to the debugger, wherein when an access address corresponding to the debug cache coherency operation hits a cache line in a cache of the first interconnect master, the debug cache coherency response includes a previous coherency state of the cache line.

12. The method of claim 11 , wherein the processing the debug cache coherency operation comprises selectively transitioning the previous coherency state of the cache line to a new coherency state.

13. The method of claim 10 , further comprising: asserting a trigger signal in response to occurrence of a specified debug event, wherein the providing the debug cache coherency operation to the first interconnect master is performed in response to the asserting the trigger signal.

14. The method of claim 10 , wherein the debug cache coherency command defines a priority to be assigned to the debug cache coherency operation.

15. The method of claim 10 , further comprising: providing a debug translation look-aside buffer (TLB) coherency operation to the first interconnect master, wherein the debug cache coherency operation is generated in response to a debug TLB coherency command from a debugger; and providing a non-debug TLB coherency operation to the first interconnect master, wherein the non-debug TLB coherency operation is generated in response to a snooped transaction performed by the second interconnect master via the system interconnect.

16. In a data processing system having a plurality of interconnect masters coupled to a system interconnect, each of the plurality of interconnect masters comprising a cache, a method comprising: receiving a debug cache coherency command from a debugger external to the data processing system, wherein the debug cache coherency command specifies one or more of the caches of the plurality of interconnect masters and at least one cache coherency domain, and the one or more of the caches are included in the at least one cache coherency domain; generating a debug cache coherency operation in response to the debug cache coherency command; and providing the debug cache coherency operation to each of one or more of the plurality of interconnect masters whose caches were specified by the debug cache coherency command.

17. The method of claim 16 , further comprising: providing a non-debug cache coherency operation to at least one of the plurality of interconnect masters, wherein the non-debug cache coherency operation is generated in response to a snooped transaction performed via the system interconnect.

18. The method of claim 16 , further comprising: receiving a debug cache coherency response from each of the one or more of the plurality of interconnect masters which received the debug cache coherency operation.