Early Release of Resources by Proceeding to Retire Store Operations from Exception Reporting Stage but Keeping in Load/Store Queue

1. A scheduler comprising: a buffer configured to store instruction operations awaiting issue, wherein the buffer is configured to store a first store memory operation; and a retire unit coupled to the buffer, wherein the retire unit is configured to retire the first store memory operation from the buffer responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported and prior to the first store memory operation being completed, and wherein the retire unit is coupled to receive a scheduler identifier from the pipeline stage at which exceptions are reported, and wherein the retire unit is configured to identify the first store memory operation in the buffer responsive to the scheduler identifier, and wherein retiring the first store memory operation comprises releasing resources used to track the first store memory operation as a speculative operation, including resources in the buffer, wherein the first store memory operation remains represented in a queue within a load/store unit subsequent to the retiring.

2. The scheduler as recited in claim 1 , wherein the scheduler is configured to free a first entry in the queue within a load/store unit assigned to the first store memory operation responsive to retiring the first store memory operation.

3. The scheduler as recited in claim 1 wherein the buffer is configured to store a first identifier of an entry in the queue that stores data representing the first store memory operation, and wherein the scheduler is configured to issue the first identifier with the first store memory operation for execution of the first store memory operation.

4. The scheduler as recited in claim 3 wherein the scheduler is coupled to receive the first identifier from a mapper that assigns the entry to the first store memory operation when the first store memory operation is decoded and transmitted to the scheduler.

5. A processor comprising: a scheduler configured to schedule a first store memory operation to be executed, wherein the first store memory operation is assigned to a first entry in a queue in a load/store unit prior to being written to the scheduler, wherein the scheduler includes a buffer storing the first store memory operation and further storing a first identifier corresponding to the first entry; and the load/store unit coupled to receive the first identifier during execution of the first store memory operation, wherein the load/store unit comprises the queue and is configured to update the first entry responsive to the first identifier; wherein the scheduler is configured to retire the first store memory operation from the buffer responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported and prior to the first store memory operation being completed, and wherein the scheduler is coupled to receive a scheduler identifier from the pipeline stage at which exceptions are reported, and wherein the scheduler is configured to identify the first store memory operation in the buffer responsive to the scheduler identifier, and wherein retiring the first store memory operation comprises releasing resources used to track the first store memory operation as a speculative operation, including resources in the buffer; and wherein the first store memory operation remains represented in the queue within the load/store unit subsequent to the retiring.

6. The processor as recited in claim 5 further comprising a mapper coupled to the scheduler, wherein the mapper is configured to assign the first entry in the queue to the first store memory operation and to provide the first store memory operation and the first identifier to the scheduler, and wherein the scheduler is configured to allocate storage in the buffer for the first store memory operation responsive to receiving the first store memory operation from the mapper.

7. The processor as recited in claim 6 wherein the mapper is configured to reassign the first identifier to a subsequent memory operation responsive to the first store memory operation being retired.

8. The processor as recited in claim 7 wherein the scheduler is configured to allocate storage for the subsequent memory operation in response to receiving the subsequent memory operation from the mapper, and wherein the scheduler is configured to schedule the subsequent memory operation to be executed.

9. The processor as recited in claim 8 wherein the load/store unit is configured to detect that the first entry remains occupied by the first store memory operation during execution of the subsequent memory operation, and wherein the load/store unit is configured to signal a replay of the subsequent memory operation responsive to detecting that the first entry remains occupied by the first store memory operation to preserve store state corresponding to the first store memory operation in the first entry.

10. The processor as recited in claim 9 wherein the load/store unit is configured to delete the first store memory operation from the queue responsive to the first store memory operation completing.

11. The processor as recited in claim 10 wherein the load/store unit is configured not to replay the subsequent memory operation responsive to deleting the first store memory operation from the queue.

12. The processor as recited in claim 11 wherein the first store memory operation is completed by updating a data cache in the processor with store data corresponding to the first store memory operation.

13. The processor as recited in claim 11 wherein the first store memory operation is completed by enqueueing store data for transmission to an external memory.

14. A method comprising: a scheduler scheduling a first store memory operation to be executed, wherein the first store memory operation is assigned to a first entry in a queue in a load/store unit prior to being written to the scheduler, wherein the scheduler includes a buffer storing the first store memory operation and further storing a first identifier corresponding to the first entry; a load/store unit receiving the first identifier during execution of the first store memory operation, wherein the load/store unit comprises the queue; the load/store unit updating the first entry responsive to the first identifier; the scheduler retiring the first store memory operation from the buffer responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported and prior to the first store memory operation being completed, and wherein the scheduler is coupled to receive a scheduler identifier from the pipeline stage at which exceptions are reported, and wherein the scheduler is configured to identify the first store memory operation in the buffer responsive to the scheduler identifier, and wherein retiring the first store memory operation comprises releasing resources used to track the first store memory operation as a speculative operation, including resources in the buffer; and retaining data corresponding to the first store memory operation in the queue within the load/store unit subsequent to the retiring.

15. The method as recited in claim 14 further comprising: a mapper assigning the first entry in the queue to the first store memory operation; the mapper providing the first store memory operation and the first identifier to the scheduler; and the scheduler allocating storage in the buffer for the first store memory operation responsive to receiving the first store memory operation from the mapper.

16. The method as recited in claim 15 further comprising the mapper reassigning the first identifier to a subsequent memory operation responsive to the first store memory operation being retired.

17. The method as recited in claim 16 further comprising: the scheduler allocating storage for the subsequent memory operation in response to receiving the subsequent memory operation from the mapper; the scheduler scheduling the subsequent memory operation to be executed; the load/store unit detecting that the first entry remains occupied by first store memory operation during execution of the subsequent memory operation; and the load/store unit signalling a replay of the subsequent memory operation responsive to detecting that the first entry remains occupied by the first store memory operation to preserve store state corresponding to the first store memory operation in the first entry.

18. The method as recited in claim 17 further comprising the load/store unit deleting the first store memory operation from the queue responsive to the first store memory operation completing.

19. The method as recited in claim 18 further comprising: the scheduler rescheduling the first store memory operation; and the load/store unit not replaying the subsequent memory operation responsive to deleting the first store memory operation from the queue.

20. The method as recited in claim 18 wherein the first store memory operation is completed by updating a data cache in the processor with store data corresponding to the first store memory operation.

21. The method as recited in claim 18 wherein the first store memory operation is completed by enqueueing store data for transmission to an external memory.