Displays

1. A display, comprising: a glass substrate comprising a plurality of pixels; a source driver for driving the pixels; and a gate driver, disposed on the glass substrate, for enabling the pixels, wherein the gate driver has (N+1) shift registers, N is a positive integer, and the nth shift register comprises: an input unit for receiving an output signal of the (n−1) th shift register of the gate driver, the input unit including: a first transistor, wherein a control terminal of the first transistor receives the output signal of the (n−1) th shift register of the gate driver, and a first terminal of the first transistor is coupled to the control terminal of the first transistor; an output unit, coupled to the input unit, for receiving an M th clock signal and outputting an output signal of the n th shift register, wherein M is equal to 1 when n is an odd number, and M is equal to 2 when n is an even number, and the output unit includes: a third transistor, wherein a control terminal of the third transistor is coupled to a second terminal of the first transistor, a first terminal of the third transistor receives the M th clock signal, and a second terminal of the third transistor outputs the output signal of the n th shift register, wherein M is equal to 1 when n is the odd number, and M is equal to 2 when n is the even number; and a first capacitor, wherein a first terminal of the first capacitor is coupled to the control terminal of the third transistor, and a second terminal of the first capacitor is coupled to the second terminal of the third transistor; an output pull-down unit, coupled to the output unit, for receiving a low operation voltage, the output pull-down unit including: a second transistor, wherein a first terminal of the second transistor is coupled to the second terminal of the first transistor, and a second terminal of the second transistor receives the low operation voltage; and a fourth transistor, wherein a control terminal of the fourth transistor is coupled to a control terminal of the second transistor, a first terminal of the fourth transistor is coupled to the second terminal of the third transistor, and a second terminal of the fourth transistor receives the low operation voltage; and a threshold voltage memory unit, coupled to the input unit and the output pull-down unit, for receiving the low operation voltage and an output signal of the (n+1) th shift register of the gate driver, the threshold voltage memory unit including: a fifth transistor formed on the glass substrate, wherein a control terminal of the fifth transistor is coupled to the first terminal of the first transistor, a first terminal of the fifth transistor is coupled to the control terminal of the second transistor, and a second terminal of the fifth transistor receives the low operation voltage; a second capacitor, wherein a first terminal of the second capacitor is coupled to the first terminal of the fifth transistor, and a second terminal of the second capacitor is coupled to the second terminal of the fifth transistor; a sixth transistor formed on the glass substrate, wherein a control terminal of the sixth transistor is coupled to a first terminal of the sixth transistor, which receives the output signal of the (n+1) th shift register, and a second terminal of the sixth transistor is coupled to the first terminal of the fifth transistor; a seventh transistor formed on the glass substrate, wherein a control terminal of the seventh transistor is coupled to the first terminal of the sixth transistor, and a first terminal of the seventh transistor is coupled to the first terminal of the fifth transistor; and an eighth transistor formed on the glass substrate, wherein a control terminal of the eighth transistor is coupled to the first terminal of the fifth transistor, a first terminal of the eighth transistor is coupled to a second terminal of the seventh transistor, and a second terminal of the eighth transistor receives the low operation voltage, wherein: n is a positive integer ranging from 1 to (N+1); and when the output signal of the (n+1) th shift register is at a high voltage level, the threshold voltage memory unit turns on the output pull-down unit such that the output signal of the n th shift register is transformed into and maintained at a low voltage level, and the threshold voltage memory unit stores a characteristic voltage relating to a threshold voltage of the output pull-down unit.

2. The display according to claim 1 , wherein when the output signal of the (n+1)th shift register is at the high voltage level, the sixth transistor and the seventh transistor are turned on such that the eighth transistor, the second transistor and the fourth transistor are turned on, the second capacitor stores the characteristic voltage, and the output signal of the nth shift register is transformed into and kept at the low voltage level.

3. A display, comprising: a glass substrate comprising a plurality of pixels; a source driver for driving the pixels; and a gate driver, disposed on the glass substrate, for enabling the pixels, wherein the gate driver has (N+1) shift registers, N is a positive integer, and the nth shift register comprises: an input unit for receiving an output signal of the (n−1) th shift register of the gate driver, the input unit including: a first transistor, wherein a control terminal of the first transistor receives the output signal of the (n−1) th shift register of the gate driver, and a first terminal of the first transistor is coupled to the control terminal of the first transistor; an output unit, coupled to the input unit, for receiving an M th clock signal and outputting an output signal of the n th shift register, wherein M is equal to 1 when n is an odd number, and M is equal to 2 when n is an even number, and the output unit includes: a third transistor, wherein a control terminal of the third transistor is coupled to a second terminal of the first transistor, a first terminal of the third transistor receives the M th clock signal, and a second terminal of the third transistor outputs the output signal of the n th shift register, wherein M is equal to 1 when n is the odd number, and M is equal to 2 when n is the even number; and a first capacitor, wherein a first terminal of the first capacitor is coupled to the control terminal of the third transistor, and a second terminal of the first capacitor is coupled to the second terminal of the third transistor; an output pull-down unit, coupled to the output unit, for receiving a low operation voltage, the output pull-down unit including: a second transistor, wherein a first terminal of the second transistor is coupled to the second terminal of the first transistor, and a second terminal of the second transistor receives the low operation voltage; and a fourth transistor, wherein a control terminal of the fourth transistor is coupled to a control terminal of the second transistor, a first terminal of the fourth transistor is coupled to the second terminal of the third transistor, and a second terminal of the fourth transistor receives the low operation voltage; and a threshold voltage memory unit, coupled to the input unit and the output pull-down unit, for receiving the low operation voltage, an output signal of the (n+1) th shift register of the gate driver, and an output signal of the (n+2) th shift register of the gate driver, the threshold voltage memory unit including: a fifth transistor formed on the glass substrate, wherein a control terminal of the fifth transistor is coupled to the first terminal of the first transistor, a first terminal of the fifth transistor is coupled to the control terminal of the second transistor, and a second terminal of the fifth transistor receives the low operation voltage; a second capacitor, wherein a first terminal of the second capacitor is coupled to the first terminal of the fifth transistor, and a second terminal of the second capacitor is coupled to the second terminal of the fifth transistor; a sixth transistor formed on the glass substrate, wherein a control terminal of the sixth transistor is coupled to a first terminal of the sixth transistor, which receives the output signal of the (n+1) th shift register, and a second terminal of the sixth transistor is coupled to the first terminal of the fifth transistor; a seventh transistor formed on the glass substrate, wherein a control terminal of the seventh transistor receives the output signal of the (n+2) th shift register, and a first terminal of the seventh transistor is coupled to the first terminal of the fifth transistor; an eighth transistor formed on the glass substrate, wherein a control terminal of the eighth transistor is coupled to the first terminal of the fifth transistor, and a first terminal of the eighth transistor is coupled to a second terminal of the seventh transistor; and a ninth transistor formed on the glass substrate, wherein a control terminal of the ninth transistor is coupled to a second terminal of the eighth transistor and a first terminal of the ninth transistor, and a second terminal of the ninth transistor receives the low operation voltage, wherein: n is a positive integer ranging from 1 to (N+1); when the output signal of the (n+1) th shift register is at a high voltage level, the threshold voltage memory unit turns on the output pull-down unit such that the output signal of the n th shift register is transformed into and maintained at a low voltage level; and when the output signal of the (n+2) th shift register is at the high voltage level, the threshold voltage memory unit stores a characteristic voltage relating to a threshold voltage of the output pull-down unit.

4. The display according to claim 3 , wherein: when the output signal of the (n+1)th shift register is at the high voltage level, the sixth transistor is turned on such that the eighth transistor, the second transistor and the fourth transistor are turned on, and the output signal of the nth shift register is transformed into and kept at the low voltage level; and when the output signal of the (n+2)th shift register is at the high voltage level, the seventh transistor is turned on and the second capacitor stores the characteristic voltage.

5. A display, comprising: a glass substrate comprising a plurality of pixels; a source driver for driving the pixels; and a gate driver, disposed on the glass substrate, for enabling the pixels, wherein the gate driver has (N+1) shift registers, N is a positive integer, and the nth shift register comprises: an input unit for receiving an output signal of the (n−1)th shift register of the gate driver; an output unit, coupled to the input unit, for receiving an Mth clock signal and outputting an output signal of the nth shift register, wherein M is equal to 1 when n is an odd number, and M is equal to 2 when n is an even number; a first output pull-down unit, coupled to the output unit, for receiving a low operation voltage; a second output pull-down unit, coupled to the output unit, for receiving the low operation voltage; a first threshold voltage memory unit, coupled to the input unit and the first output pull-down unit, for receiving a first operation voltage, the low operation voltage, an output signal of the (n+1)th shift register of the gate driver, and an output signal of the (n+2)th shift register of the gate driver; and a second threshold voltage memory unit, coupled to the input unit and the second output pull-down unit, for receiving a second operation voltage, the low operation voltage, the output signal of the (n+1)th shift register and the output signal of the (n+2)th shift register, wherein: n is a positive integer ranging from 1 to (N+1); when the output signal of the (n+1)th shift register is at a high voltage level, the first operation voltage is at the high voltage level, the second operation voltage is at low voltage level, and the first threshold voltage memory unit turns on the first output pull-down unit such that the output signal of the nth shift register is transformed into and kept at the low voltage level in an even-numbered frame period; and the first operation voltage is at the low voltage level, the second operation voltage is at the high voltage level, and the second threshold voltage memory unit turns on the second output pull-down unit such that the output signal of the nth shift register is transformed into and maintained at the low voltage level in an odd-numbered frame period; and when the output signal of the (n+2)th shift register is at the high voltage level, the first threshold voltage memory unit stores a first characteristic voltage relating to a threshold voltage of the first output pull-down unit in the even-numbered frame period, and the second threshold voltage memory unit stores a second characteristic voltage relating to a threshold voltage of the second output pull-down unit in the odd-numbered frame period.

6. The display according to claim 5 , wherein the input unit comprises: a first transistor, wherein a control terminal of the first transistor receives the output signal of the (n−1)th shift register of the gate driver, and a first terminal of the first transistor is coupled to the control terminal of the first transistor.

7. The display according to claim 6 , wherein the output unit comprises: a third transistor, wherein a control terminal of the third transistor is coupled to a second terminal of the first transistor, a first terminal of the third transistor receives the Mth clock signal, and a second terminal of the third transistor outputs the output signal of the nth shift register, wherein M is equal to 1 when n is the odd number, and M is equal to 2 when n is the even number; and a first capacitor, wherein a first terminal of the first capacitor is coupled to the control terminal of the third transistor, and a second terminal of the first capacitor is coupled to the second terminal of the third transistor.

8. The display according to claim 7 , wherein the first output pull-down unit comprises: a second transistor, wherein a first terminal of the second transistor is coupled to the second terminal of the first transistor, and a second terminal of the second transistor receives the low operation voltage; and a fourth transistor, wherein a control terminal of the fourth transistor is coupled to a control terminal of the second transistor, a first terminal of the fourth transistor is coupled to the second terminal of the third transistor, and a second terminal of the fourth transistor receives the low operation voltage.

9. The display according to claim 8 , wherein the second output pull-down unit comprises: a fifth transistor, wherein a first terminal of the fifth transistor is coupled to the second terminal of the first transistor, and a second terminal of the fifth transistor receives the low operation voltage; and a sixth transistor, wherein a control terminal of the sixth transistor is coupled to a control terminal of the fifth transistor, a first terminal of the sixth transistor is coupled to the second terminal of the third transistor, and a second terminal of the sixth transistor receives the low operation voltage.

10. The display according to claim 9 , wherein the first threshold voltage memory unit comprises: a seventh transistor formed on the glass substrate, wherein a control terminal of the seventh transistor is coupled to the first terminal of the first transistor, a first terminal of the seventh transistor is coupled to the control terminal of the second transistor, and a second terminal of the seventh transistor receives the low operation voltage; a second capacitor, wherein a first terminal of the second capacitor is coupled to the first terminal of the seventh transistor, and a second terminal of the second capacitor is coupled to the second terminal of the seventh transistor; an eighth transistor formed on the glass substrate, wherein a control terminal of the eighth transistor receives the output signal of the (n+1)th shift register, a first terminal of the eighth transistor receives the first operation voltage, and a second terminal of the eighth transistor is coupled to the first terminal of the seventh transistor; a ninth transistor formed on the glass substrate, wherein a control terminal of the ninth transistor receives the output signal of the (n+2)th shift register, and a first terminal of the ninth transistor is coupled to the first terminal of the seventh transistor; a tenth transistor formed on the glass substrate, wherein a control terminal of the tenth transistor is coupled to the first terminal of the seventh transistor, and a first terminal of the tenth transistor is coupled to a second terminal of the ninth transistor; and an eleventh transistor formed on the glass substrate, wherein a control terminal of the eleventh transistor is coupled to a second terminal of the tenth transistor and a first terminal of the eleventh transistor, and a second terminal of the eleventh transistor receives the low operation voltage.

11. The display according to claim 10 , wherein: in the even-numbered frame period, the first operation voltage is at the high voltage level; when the output signal of the (n+1)th shift register is at the high voltage level, the eighth transistor is turned on such that the tenth transistor, the second transistor and the fourth transistor are turned on, and the output signal of the nth shift register is transformed into and kept at the low voltage level; and when the output signal of the (n+2)th shift register is at the high voltage level, the ninth transistor is turned on, and the second capacitor stores the first characteristic voltage.

12. The display according to claim 9 , wherein the second threshold voltage memory unit comprises: a twelfth transistor formed on the glass substrate, wherein a control terminal of the twelfth transistor is coupled to the first terminal of the first transistor, a first terminal of the twelfth transistor is coupled to the control terminal of the fifth transistor, and a second terminal of the twelfth transistor receives the low operation voltage; a third capacitor, wherein a first terminal of the third capacitor is coupled to the first terminal of the twelfth transistor, and a second terminal of the third capacitor is coupled to the second terminal of the twelfth transistor; a thirteenth transistor formed on the glass substrate, wherein a control terminal of the thirteenth transistor receives the output signal of the (n+1)th shift register, a first terminal of the thirteenth transistor receives the second operation voltage, and a second terminal of the thirteenth transistor is coupled to the first terminal of the twelfth transistor; a fourteenth transistor formed on the glass substrate, wherein a control terminal of the fourteenth transistor receives the output signal of the (n+2)th shift register, and a first terminal of the fourteenth transistor is coupled to the first terminal of the twelfth transistor; a fifteenth transistor formed on the glass substrate, wherein a control terminal of the fifteenth transistor is coupled to the first terminal of the fourteenth transistor, and a first terminal of the fifteenth transistor is coupled to a second terminal of the fourteenth transistor; and a sixteenth transistor formed on the glass substrate, wherein a control terminal of the sixteenth transistor is coupled to a second terminal of the fifteenth transistor and a first terminal of the sixteenth transistor, and a second terminal of the sixteenth transistor receives the low operation voltage.

13. The display according to claim 12 , wherein: in the odd-numbered frame period, the second operation voltage is at the high voltage level; when the output signal of the (n+1)th shift register is at the high voltage level, the thirteenth transistor is turned on such that the fifteenth transistor, the fifth transistor and the sixth transistor are turned on, and the output signal of the nth shift register is transformed into and kept at the low voltage level; and when the output signal of the (n+2)th shift register is at the high voltage level, the fourteenth transistor is turned on, and the third capacitor stores the second characteristic voltage.

14. The display according to claim 5 , wherein the nth shift register further comprises: a seventeenth transistor formed on the glass substrate, wherein a control terminal of the seventeenth transistor receives the output signal of the (n+1)th shift register, a first terminal of the seventeenth transistor is coupled to a second terminal of the first transistor, and a second terminal of the seventeenth transistor receives the low operation voltage; and an eighteenth transistor formed on the glass substrate, wherein a control terminal of the eighteenth transistor receives the output signal of the (n+1)th shift register, a first terminal of the eighteenth transistor is coupled to a second terminal of the third transistor, and a second terminal of the eighteenth transistor receives the low operation voltage.

15. A display, comprising: a glass substrate comprising a plurality of pixels; a source driver for driving the pixels; and a gate driver, disposed on the glass substrate, for enabling the pixels, wherein the gate driver has (N+1) shift registers, N is a positive integer, and the nth shift register comprises: an input unit for receiving an output signal of the (n−1)th shift register of the gate driver, the input unit including: a first transistor, wherein a control terminal of the first transistor receives the output signal of the (n−1)th shift register of the gate driver, and a first terminal of the first transistor is coupled to the control terminal of the first transistor; an output unit, coupled to the input unit, for receiving an Mth clock signal and outputting an output signal of the nth shift register, wherein M is equal to 1 when n is an odd number, and M is equal to 2 when n is an even number, and the output unit includes: a third transistor, wherein a control terminal of the third transistor is coupled to a second terminal of the first transistor, a first terminal of the third transistor receives the Mth clock signal, and a second terminal of the third transistor outputs the output signal of the nth shift register, wherein M is equal to 1 when n is the odd number, and M is equal to 2 when n is the even number; and a first capacitor, wherein a first terminal of the first capacitor is coupled to the control terminal of the third transistor, and a second terminal of the first capacitor is coupled to the second terminal of the third transistor; an output pull-down unit, coupled to the output unit, for receiving a low operation voltage, the output pull-down unit including: a ninth transistor formed on the glass substrate, wherein a control terminal of the ninth transistor receives the output signal of the (n+1)th shift register, a first terminal of the ninth transistor is coupled to the second terminal of the first transistor, and a second terminal of the ninth transistor receives the low operation voltage; and a tenth transistor formed on the glass substrate, wherein a control terminal of the tenth transistor receives the output signal of the (n+1)th shift register, a first terminal of the tenth transistor is coupled to the second terminal of the third transistor, and a second terminal of the tenth transistor receives the low operation voltage; and a threshold voltage memory unit, coupled to the input unit and the output pull-down unit, for receiving the low operation voltage and an output signal of the (n+1)th shift register of the gate driver, wherein: n is a positive integer ranging from 1 to (N+1); and when the output signal of the (n+1)th shift register is at a high voltage level, the threshold voltage memory unit turns on the output pull-down unit such that the output signal of the nth shift register is transformed into and maintained at a low voltage level, and the threshold voltage memory unit stores a characteristic voltage relating to a threshold voltage of the output pull-down unit.

16. A display, comprising: a glass substrate comprising a plurality of pixels; a source driver for driving the pixels; and a gate driver, disposed on the glass substrate, for enabling the pixels, wherein the gate driver has (N+1) shift registers, N is a positive integer, and the nth shift register comprises: an input unit for receiving an output signal of the (n−1)th shift register of the gate driver, the input unit including: a first transistor, wherein a control terminal of the first transistor receives the output signal of the (n−1)th shift register of the gate driver, and a first terminal of the first transistor is coupled to the control terminal of the first transistor; an output unit, coupled to the input unit, for receiving an Mth clock signal and outputting an output signal of the nth shift register, wherein M is equal to 1 when n is an odd number, and M is equal to 2 when n is an even number, and the output unit includes: a third transistor, wherein a control terminal of the third transistor is coupled to a second terminal of the first transistor, a first terminal of the third transistor receives the Mth clock signal, and a second terminal of the third transistor outputs the output signal of the nth shift register, wherein M is equal to 1 when n is the odd number, and M is equal to 2 when n is the even number; and a first capacitor, wherein a first terminal of the first capacitor is coupled to the control terminal of the third transistor, and a second terminal of the first capacitor is coupled to the second terminal of the third transistor; an output pull-down unit, coupled to the output unit, for receiving a low operation voltage, the output pull-down unit including: a tenth transistor formed on the glass substrate, wherein a control terminal of the tenth transistor receives the output signal of the (n+1)th shift register, a first terminal of the tenth transistor is coupled to the second terminal of the first transistor, and a second terminal of the tenth transistor receives the low operation voltage; and an eleventh transistor formed on the glass substrate, wherein a control terminal of the eleventh transistor receives the output signal of the (n+1)th shift register, a first terminal of the eleventh transistor is coupled to the second terminal of the third transistor, and a second terminal of the eleventh transistor receives the low operation voltage; and a threshold voltage memory unit, coupled to the input unit and the output pull-down unit, for receiving the low operation voltage, an output signal of the (n+1)th shift register of the gate driver, and an output signal of the (n+2)th shift register of the gate driver, wherein: n is a positive integer ranging from 1 to (N+1); when the output signal of the (n+1)th shift register is at a high voltage level, the threshold voltage memory unit turns on the output pull-down unit such that the output signal of the nth shift register is transformed into and maintained at a low voltage level; and when the output signal of the (n+2)th shift register is at the high voltage level, the threshold voltage memory unit stores a characteristic voltage relating to a threshold voltage of the output pull-down unit.