Method and Apparatus for Resolving Clock Management Issues in Emulation Involving Both Interpreted and Translated Code

1. A method for resolving clock management issues in emulation of a target system on a host system, the method comprising: emulating a first set of code instructions of a target program to generate first set of emulated instructions that emulate a first component of the target system on the host system; emulating a second set of instructions of the target program to generate second set of emulated instructions that emulate a second component of the target system on the host system; executing the first set of emulated instructions, wherein execution of the first set of emulated instructions is based on a first clock; executing the second set of emulated instructions, wherein execution of the second set of emulated instructions is based on a second clock; and adjusting the first or second clock, an execution of the first or second set of emulated instructions or a memory access to maintain a desired synchronization between the first and second sets of emulated instructions.

2. The method of claim 1 wherein the first clock is a fixed clock and the second clock is a variable clock.

3. The method of claim 2 wherein adjusting the first or second clock, rate of execution of the first or second set of emulated instructions or memory access includes holding back execution of the second set of emulated instructions or memory access when the second clock is running faster than the first clock.

4. The method of claim 2 wherein the second set of emulated instructions use an emulated cycle counter to estimate how long an operation will take.

5. The method of claim 4 wherein timing of the execution of the second set of emulated instructions is keyed to the variable clock and timing of the execution of the first set of emulated instructions is keyed to the fixed clock.

6. The method of claim 3 wherein holding back execution of the second set of emulated instructions or memory access when the second clock is running faster than the first clock includes executing a predetermined number of emulated cycles, checking to see if the variable clock is running faster than the fixed clock; and if the variable clock is running faster than the fixed clock, holding back the variable clock.

7. The method of claim 1 wherein the host system includes a cell processor having a power processor element and a plurality of synergistic processor elements coupled to the power processor element.

8. The method of claim 1 wherein the first component is an emotion engine and the second component is an input/output processor coupled to the emotion engine.

9. The method of claim 1 wherein, in a situation where there is not sufficient time for the host device to complete an emulated instruction operation before a frame must be presented to a display device, adjusting the first or second clock, an of execution of the first or second emulated sets of instructions or a memory access to maintain a desired synchronization between the first and second sets of emulated instructions includes repeating a current frame to provide additional time to complete the translated instruction operation.

10. The method of claim 1 wherein adjusting the first or second clock, an of execution of the first or second sets of emulated instructions or a memory access to maintain a desired synchronization between the first and second sets of emulated instructions includes: looking up an efficiency of use of the second component by one or more portions of the target program and adjusting the second clock rate based on the efficiency of use.

11. The method of claim 1 wherein adjusting the first or second clock, an of execution of the first or second sets of emulated instructions or a memory access to maintain a desired synchronization between the first and second sets of emulated instructions includes: determining whether an emulated event may time out due to a difference in between a rate of the first clock and a rate of the second clock; and adjusting the first clock rate or execution of the second set of emulated instructions to avoid a time-out of the emulated event.

12. The method of claim 11 wherein determining whether an emulated event may time out due to a difference in between a rate of the first clock and a rate of the second clock includes detecting whether the target program has set a value in a control register and then polled the control register repeatedly to wait for a result.

13. The method of claim 12 wherein adjusting the first clock rate or execution of the second set of emulated instructions to avoid the time out includes: altering the execution of emulation of the target program in a way that avoids timing out if the target program polls the register greater than a predetermined number of times.

14. The method of claim 13 wherein altering the execution of emulation of the target program includes slowing down the emulation by a sufficient margin to prevent the time-out.

15. The method of claim 13 wherein altering the execution of emulation of the target program includes not returning any response to the emulated target program until a hardware state changes.

16. The method of claim 13 wherein altering the execution of emulation of the target program includes analyzing a relevant section of the target program to determine whether a polling operation is occurring.

17. The method of claim 12 , further comprising further comprising performing functions unrelated to the time-out with emulated hardware while adjusting the first clock rate or execution of the second set of emulated instructions to avoid a time-out of the emulated event.

18. The method of claim 1 , wherein executing the translated and/or interpreted instructions includes writing one or more write instructions from a first emulated device and reading the one or more write instructions with a second emulated device, wherein adjusting the first or second clock, an of execution of the first or second sets of emulated instructions or a memory access to maintain a desired synchronization between the first and second sets of emulated instructions includes: storing the one or more write instructions in a journal in an order in which they were written and reading the one or more write instructions with the second emulated device in the order in which they were written.

19. A host system for emulating a target system, comprising: one or more processors; a memory coupled to the one or more processors; a set of processor executable instructions embodied in the memory, the processor executable instructions including instructions for implementing method for resolving clock management issues in emulation of the target system on the host system, the method including: emulating a first set of target code instructions of a target program to generate a first set of emulated instructions that emulate a first component of the target system on the host system; emulating a second set of target code instructions to generate a second set of emulated instructions that emulate a second component of the target system on the host system; executing the first set of emulated instructions, wherein execution of the first set of emulated instructions is based on a first clock; and executing the second set of emulated instructions, wherein execution of the second set of emulated instructions is based on a second clock; and adjusting the first or second clock, an of execution of the first or second set of emulated instructions or a memory access to maintain a desired synchronization between the first and second sets of emulated instructions.

20. The system of claim 19 wherein the host system includes a cell processor having a power processor element and a plurality of synergistic processor elements coupled to the power processor element.