System and Method for Maintaining the Security of Memory Contents and Computer Architecture Employing the Same

1. A secure memory system, comprising: a security control module configured to transmit a system memory secure mode signal and processor secure mode signal to place said system in a secure mode; a secure memory bridge coupled to said security control and system memory and configured to encrypt and decrypt data associated with said system memory based on a state of said system memory secure mode signal; and a boot processor coupled to said security control module and said secure memory bridge and configured to transmit requests to said secure memory bridge in said secure mode and an unsecure mode.

2. The system as recited in claim 1 wherein said security control module is further configured to transmit at least one key to said secure memory bridge.

3. The system as recited in claim 2 wherein said at least one key includes separate encryption and decryption keys.

4. The system as recited in claim 2 wherein said secure memory bridge includes: a decrypter having an output thereof coupled to an input of a first multiplexer; and an encrypter having an output thereof coupled to an input of a second multiplexer, said system memory secure mode signal provided to said first and second multiplexers and said at least one key provided to said encrypter and said decrypter.

5. The system as recited in claim 1 wherein said security control module is further configured to transmit a key to said boot processor.

6. The system as recited in claim 5 wherein said boot processor further includes an on-chip emulator/in-chip emulator and a Joint Test Action Group controller coupled thereto, said on-chip emulator/in-chip emulator configured to receive and employ said key for communication with said secure memory bridge.

7. The system as recited in claim 1 further comprising a secure read-only memory and an unsecure read-only memory configured for respective use in said secure and unsecure modes.

8. A method of maintaining the security of memory contents, comprising: configuring a computer system in which a system memory containing said contents is located in a secure mode; transmitting a system memory secure mode signal to a secure memory bridge in said system; transmitting a processor secure mode signal to a boot processor in said system; transmitting encryption and decryption keys to said secure memory bridge; placing an encrypter and a decrypter in said secure memory bridge in data paths therein; and causing said secure memory bridge to respond to write and read requests using said encryption and decryption keys.

9. The method as recited in claim 8 wherein said configuring comprises setting a secure mode I/O pin to a particular binary value.

10. The method as recited in claim 8 further comprising applying a reset signal to said system.

11. The method as recited in claim 8 further comprising transmitting a key to a boot processor in said system.

12. The method as recited in claim 11 further comprising causing said boot processor to employ a secure ROM to execute instructions stored therein.

13. The method as recited in claim 8 wherein said boot processor further comprises an on-chip emulator/in-chip emulator and said method further comprising employing said key for communication with said secure memory bridge.

14. The method as recited in claim 8 further comprising placing other bus masters in said secure mode as a prelude to post-boot system operation.

15. A secure memory system, comprising: a bus interconnect; a boot processor coupled to, and configured to be a bus master for, said a bus interconnect; a secure memory bridge coupled to, and configured to be a bus slave for, said bus interconnect and configured to encrypt and decrypt data associated with said system memory based on a state of a system memory secure mode signal, said boot processor further configured to transmit requests to said secure memory bridge in a secure mode and an unsecure mode; system memory coupled to said secure memory bridge; a secure read-only memory and an unsecure read-only memory coupled to, and configured to be bus slaves for, said bus interconnect; a secure bus bridge coupled to, and configured to be a bus slave for, said bus interconnect; a security control module coupled to said secure bus bridge and configured to transmit said system memory secure mode signal and processor secure mode signal to place said system in said secure mode; and an external device controller coupled to, and configured to be a bus master for, said bus interconnect.

16. The system as recited in claim 15 wherein said security control module is further configured to transmit at least one key to said secure memory bridge.

17. The system as recited in claim 16 wherein said at least one key includes separate encryption and decryption keys.

18. The system as recited in claim 16 wherein said secure memory bridge includes: a decrypter having an output thereof coupled to an input of a first multiplexer; and an encrypter having an output thereof coupled to an input of a second multiplexer, said system memory secure mode signal provided to said first and second multiplexers and said at least one key provided to said encrypter and said decrypter.

19. The system as recited in claim 15 wherein said security control module is further configured to transmit a key to said boot processor.

20. The system as recited in claim 19 wherein said boot processor further includes an on-chip emulator/in-chip emulator and a Joint Test Action Group controller coupled thereto, said on-chip emulator/in-chip emulator configured to receive and employ said key for communication with said secure memory bridge.